UVM Verification Environment Development for GPIO DUT with Documentation

Project Goal:
- Development of a complete UVM verification environment for an existing GPIO DUT
- Creation of comprehensive documentation
- Generation of golden reference outputs

Main Tasks:
- Design and implement UVM verification components:
• UVM Test bench architecture
• Sequencer for test stimulus generation
• Driver for DUT interface handling
• Monitor for capturing DUT transactions
• Scoreboard for result verification
• Controller implementation
- Create detailed documentation including:
• Block diagram showing DUT architecture
• Input/output port specifications
• Functional description
• UVM component architecture and interactions
- Develop Python scripts for golden output generation

Required Skills:
- SystemVerilog and UVM methodology expertise
- Experience with GPIO verification
- Python programming skills
- Technical documentation capabilities

Expected Deliverables:
- Complete UVM verification environment
- Comprehensive documentation with block diagrams
- Python scripts for golden output generation
- Verification test cases