Upgrade Post project
AD
Banglore
available

Last update: 04.10.2011

vlsi design and verification engineer.

Graduation: not provided
Hourly-/Daily rates: show
Languages: English (Limited professional) | Hindi (Limited professional)

Keywords

Skills

I am a Vlsi Engineer with knowledge of Verilog ,Syytem verilog , Ovm Methodology, Verilog HDL-AMS(Analog Mix-signal).
worked on tools Questasim and modelsim.

Project history

I have done projects on Vlsi like Traffic light controller, constrained randomization of AMBA, AHB,APB protocols, coffee dispensing machine.Simulation and layout of an inverter,synthesizing the multiplexer code.

Local Availability

Only available in these countries: India
i am a fresher so i am 100% and all the time available .
Profileimage by Anonymous profile, vlsi design and verification engineer. vlsi design and verification engineer.
Register