Description
We are looking for a
Custom layout designer for advanced node test chip development (m/f)
Reference: -en
Start: 09/16
Duration: 3 MM++
Place: in Saxony
Branch: Herstellung von sonstigen elektronischen Bauelementen
Your tasks:
- Layout of complex memory IP for process development
- Bottom up layout based on custom design schematics
- Schematic driven layout of assigned circuits with the Cadence Virtuoso tool suite
- Completion of the layout using LVS and DRC including colouring and fill
- Handling layout revision caused by post-layout iterations with design as well as technology changes (Booleans, design rules, PDK)
- Preparation and co-presentation at layout reviews
Your qualifications
- Familiar with the Cadence Virtuoso tool suite
- Experience with Mentor Calibre LVS and DRC tools
- Know-how regarding advanced node CMOS technologies (equal or less than 40nm)
Skills:
- Hardware developer
Keywords: Hardwareentwickler