System Verilog/Methodology Engineer

California  ‐ Onsite
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Description

12 month contract. You will be responsible for becoming a subject matter expert and go-to person for other members of your team. The environment is fast-paced and requires cross-functional interaction on a daily basis so good communication, planning and execution skills are a must. Validation Team is part of the central SoC digital hardware organization responsible for the overall quality of the SoC silicon. The Validation team works closely with architects, designers, verification engineers, software engineers, and customers

Minimum Qualifications: The candidate is to perform the following technical discipline encompassing these languages and/or methodologies: System Verilog OVM/UVM including Test Bench Architecture VIP Development Software/Hardware Debug/problem Solving skills Programming and Scripting skills, with C/C++, Perl

Education: Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering

Start date
ASAP
Duration
12 months
From
Infinite Resources, Inc.
Published at
24.02.2017
Project ID:
1294465
Contract type
Freelance
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