Description
Mixed Signal verification engineer
Nijmegen, Netherlands
6 month contract (extendable)
€40-50/hour
The Company
A leading semiconductor company.
The Role
- Verification Engineer for Mixed Signal product or IP development; specify, plan, execute and report V&V simulations of products and IP to proof the functional and structural correctness before IC Mask Ordering.
- Define and apply appropriate verification strategies, at different abstraction levels.
- Definition and maintenance of the V&V simulation infrastructure, including generation of V&V specifications, test benches, Verification IP, test cases, and reports.
- Targeting re-use of V&V components, eg for regression and for 'out-of-the-box' V&V as part of IP delivery.
- Works closely together with Architects (System, IC, SW) to understand the overall product concept and to discuss the V&V approach and results.
- Supports the V&V Engineers in setting up their detailed test specifications and plan, analysing defect causes and defect prevention measures.
- Participates in Change Control Board, simulations, reviews, inspections, walkthroughs from the V&V perspective
- Analyzing defect causes and suggesting defect prevention measures
- Definition of the V&V simulation infrastructure, including, test benches, Verification IP, lab test infrastructure (both HW and SW), prototyping (FPGA and/or virtual prototyping).
- Hands-on test activities on prototype or first silicon
- Coaching/training Verification and Validation engineers
- Targeting re-use of V&V components, Infrastructure, tooling and SW
The Individual
- Excellent communicator and team player, willing to be in testing role.
- At least 5 years of working experience in AMS IC Design/Verification and a master degree (or similar level acquired by experience) in electronics or information engineering.
- To ease the discussion with the architects and developers, knowledge of AMS IC development process, flows and IC application is a must.
- Experienced in and affinity with AMS modelling and simulation methods, different V&V strategies, levels and tools.
- Experience with digital verification is preferred, UVM, coverage driven, PSL;
- Experience with Analog Mixed signal design is a big plus; at least some fundamental knowledge of analog design principles and tooling.
- Good skills in Verilog (AMS), System Verilog and/or VHDL, Tcl and/or Perl, Python, Linux/Unix Scripting,
- Experience with SystemC, XML, Ocean, Cadence EDA tooling is a plus.