Description
6+Month Contract
Boston, MA Region
Summary:
- Implementation and verification of DFT architecture and features
- Scan/Jtag/boundary scan insertion and ATPG pattern generation
- ATPG patterns verification with gate level simulation
- Test coverage and test cost reduction analysis
- Post silicon support to ensure successful bringup and enhance yield learning
Required Experience:
- Ability to debug large complex scan drc and gate level simulation issues at SoC level
- Understanding of Design For Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST, ? etc)
- Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
- Experience with VCS simulation tool, Perl/Shell Scripting and Verilog RTL design
- Excellent oral, written and interpersonal communication skills