Description
Digital Design/Verification/Back End Engineer - 6mth contract - Belgium
Position Description
- As digital design/verification/Back End engineer you will be part of a multi-functional product development team under the lead of a project leader and will be responsible for a digital sub-part of a mixed signal SoC (System on Chip).
- You will work with modern methodologies using EDA tools from established tool vendors (Cadence, Mentor, Synopsys).
- Digital Design: You are involved in translation of customer requirements into HW representation using processes and IP's, and will develop RTL code using Verilog
- Digital Verification: You will verify the digital part of mixed-signal SoC using Cadence Xcelium.
- Digital Back End: You will convert the digital RTL code to a gate level netlist for integration in a mixed-signal ASIC.
- This will involve synthesis, static timing analysis, DFT, scan chain test pattern generation (ATPG) and sign-off.
- The project is an ASSP for battery management, using high voltage low power mixed-signal technologies.
Position Requirements
- Experience in HDL languages (Verilog, SystemVerilog, VHDL)
- Experience in digital design for integrated circuits.
- Expertise in the requested steps of the SOC design flow - RTL design, simulation, verification, DFT, sign off
- (Cadence, Synopsys and Mentor EDA tools)
- Scripting programming skills: TCL, PERL, Linux Shell Scripting, etc
- Understanding of CMOS technology
- Experience in low power design is a plus
If this exciting opportunity could be of interest, please contact me ASAP to discuss further.