Description
My client are looking for a UVM Verification Engineer for a long-term assignment.
Required skills
- RTL Verification
- Linux
- UVM
Preferred skills
- MATLAB Simulink
Languages
English (Proficient)
Assignment description
The expert should have extensive experience of architecting and implementing Verification test benches for complex IP & module level design.
Ideal candidates should have following skills:
- Previous experience of SystemVerilog and UVM Methodology for RTL verification (test case creation and/or testbench creation)
- Datapath verification of signal processing designs in Linux environment
- Previous experience in MATLAB Simulink is not mandatory but is seen as big advantage
Work can be done remotely.