Digital Design Engineer (FPGA, ASIC, 100% Remote)

Job type:
remote
Start date:
asap
Duration:
6 months (extension possible)
From:
Optimus Search GmbH
Location:
Leuven
Published at:
02/23/2021
Country:
flag_no Belgium
Contact person:
Luke Rainford
Project ID:
2056453


We've partnered with a technical development firm who are searching for an experienced digital ASIC/FPGA engineer. Main activity will be RTL implementation (either in Verilog or VHDL) and verification (in System-Verilog) of components for a Digital Baseband for a radio system.

The specification of the to-be-implemented components is usually in Matlab / Python.

Requirements:
- 5+ years experience with Verilog (or VHDL) experience for RTL implementation, both for FPGA and ASIC
- SystemVerilog experience for testbench development
- Good understanding of Matlab / Python and able to use it for integration in the testbenches (to make it self-checking).
- Able to document the implemented components.