Description
Brief description:
The Digital CMOS IC Layout engineer receives his/her instructions from the design manager and/or from the project leader. He/she decides on technical aspects of the test items and needs to consult the line manager if planning or budget consequences arise from such decisions. The Digital CMOS IC Verification engineer works according to the BU-ID verification way-of-working, but different insights and methods are encouraged.
Requirements:
The ideal candidate should have the following competencies and skills in security aware floorplanning, setup of CTS, place & route, timing optimization, timing closure, STA, formal verification, physical verification, and more. You should also be experience with the following tools, Encounter, QRC, ETS, EPS, PVS, Conformal, def_checker and more.