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Engineer for RTL design with VHDL (m/f)

Saxony  ‐ Onsite
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Keywords

Description


We are looking for a
Engineer for RTL design with VHDL (m/f)

Reference: -en
Start: 05/14
Duration: 4 MM++
Place: in Saxony
Branch: Herstellung von bestückten Leiterplatten

Your tasks:
  • RTL design using VHDL and Verilog
  • RTL verification
  • Power verification


Your qualifications
  • Knowledge with RTL Design
  • Experiences with VHDL
  • FPGA



Skills:
- Software developer
- Hardware developer
Start date
05/14
Duration
4 MM++
(extension possible)
From
Hays AG
Published at
16.04.2014
Contact person:
Kerstin Sieber
Project ID:
696676
Contract type
Freelance
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