Description
We are looking for a
Verification Engineer (m/f)
Reference: -en
Start: asap
Duration: 6 MM++
Place: in Styria
Branch: Elektronik
Your tasks:
- Writing Test Cases at system Level for Mixed-mode chip
- Being able to comprehend technical specification
- Writing C++ programs for Micro-controller based chip
- Write verification documents like verification reports
Your qualifications
- Experienced in using System Verilog including (SV assertions)
- Experienced in using UVM Methodology
- Familiar with version control tools (DesignSync, ClearCase, …)
- Experience with ePlanner, eManager is a plus
- Knowledge of Verilog and PSL is a plus
- C++
Skills:
- Software developer