Description
* BS degree in Electrical or Computer Systems Engineering or Computer Science + 7 years or Masters + 4 years practical experience in design verification.Experience Required:
* Development and execution of pre-silicon verification test plans
* Development of verification environment and infrastructure
* Verification of complex microprocessor SOC's (preferably with ARM or multiple architectures)
* Development of directed and random verification tests to validate IP/chip function
* Proficiency in debug of Verilog RTL and gate-level simulation, at the IP and/or chip-level
* Mastery of industry standard simulation tools (VCS, Verdi)
* Mastery of at least one verification language (preferably SV/UVM, though the following also acceptable: SV/VMM, SV, C++, SystemC, Vera, E)
* Mastery of a scripting language (Shell, Perl, Python, Ruby)
* Verification functional coverage using industry standard coverage analysis tools/methods.
* Ability to replicate functional issues found post-silicon; review/enhance tests to verify bug fixes