Description
This design engineer will be a part of a team responsible for the development of our client's next generation of PCI Express switches.* Micro architecture refinement and specification documentation
* Logic design and Verilog RTL development
* Shared responsibility for design-for-test and timing-closure in a COT flow
* Shared responsibility for verification of the design (block and chip level) leading to ASIC tape-outs
* Support for emulation activities
* Validation of early samples
Required Experience:
* 5+ years of industry chip design experience including successful completion of high speed and complex IC's.
* Verilog RTL coding skills, synthesis, and timing closure in a ASIC or COT flow.
* Enthusiastic and motivated to learn and pick up newer VLSI/ASIC design skills, in a fast paced environment.
* Experience using Perl or other such scripting to solve various aspects of design leading to tape-out
* Experience with PCI Express (preferred), DDR Controller (preferred) or networking protocols
* Experience with 3rd party IP integration
* Lab and system level debug experience
* Excellent communication and interpersonal skills
Required Education:
BSEE/CE or equivalent; MSEE/CE preferred