Description
Responsibilities OVERALL FUNCTION:In collaboration with hardware and embedded software engineers, the FPGA Engineer will develop FPGA systems, develop Simulink behavioral models from scratch and from existing DSP IP blocks to achieve the most efficient use of FPGA structural resources. The objective is to support Meyer's goal of rapid design and development of behavioral models using Simulink for deployment onto FPGAs in our systems.
ESSENTIAL RESPONSIBILITIES:
Collaborate with engineers to develop Simulink model from scratch and from existing C source code, TI and Analog Devices DSP IP.
Support the engineering team to rapidly develop prototype models of Meyer IP from creation to validation.
Work one-on-one and in small teams to troubleshoot and debug designs after deployment.
Continually learn and exercise best practices to achieve maximum efficiency and optimization of FPGA architectures.
Job Requirements
BS EE, CS or Math required, AND 5 years direct experience, or MSEE/CS/Math and 3 years of specific, proven equivalent experience developing FPGAs using Mathworks Simulink and Xilinx Tools.
Practitioner in VHDL, Verilog.
Deploying Xilinx FPGAs into systems.
Xilinx tools: ISE, Vivado, SysGen, Active HDL, ModelSIM creation and deployment, SimuLink, Vivado, ISE, SysGen, ActiveHDL or ModelSIM.
BIG PLUSSES:
Experience in and/or passion for audio processing and/or acoustics, live audio concepts and equipment.
Experience designing and developing with TI or Analog Device DSPs.