Description
In this role, you will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, verification, power, timing, synthesis etc. to deliver high quality RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions. You will evaluate design options with complexity, performance, power and area in mind.Responsibilities- Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform RTL coding, function/performance simulation debug, Lint/CDC/FV/UPF checks.
- Participate in synthesis, timing/power closure and FPGA/silicon bring-up.
- Participate in test plan and coverage analysis of the block and SOC-level verification.
- Communicate and work with multi-disciplined and multi-site teams.
Minimum qualifications
- BS degree in Electrical Engineering or equivalent practical experience.
- 5 years of practical experience.
- Experience in ASIC development with Verilog or VHDL.
- Experience with ASIC design verification, synthesis, timing/power analysis and DFT.
Preferred qualifications
- MS degree in Electrical Engineering. 10 years of practical experience.
- Knowledge of high performance and low power design techniques.
- Knowledge of FPGA and emulation platforms. Knowledge of SOC architecture.
- Knowledge of assertion-based formal verification.
- Proficient with a scripting language like Perl.
- Domain knowledge in one of these areas: memory compression, fabric, coherence, cache, DRAM, PHY.