Software Developer

Past activities development and worked projects in Continental:
Part of Memory team on several projects
Integrated Memory stack in various projects
Bug fixing on various projects on any topic related to Memory stack
Implemented cdd to make sure that the lifetime of NvM is preserved
Part of Communication States and Security team
Configured security Bac delivered modules
Investigated issues for security Bac modules based on automated testing reports
Gluecode for Comprehensive Environmental Model project, multiple signal mapping

Past activities in Magna International:
Part of Lifecycle team
Refactor BswM module by the architecture.
Implemented concept for Shutdown of the Ecu which involved multiple components: EcuM, WDG, Sbc, EthTrcv, SMU.
Bug Fixing on Lifecycle which included debug sessions with the client
Fixed and maintained ZST automated testing
Implemented concept to read wakeup Pulses from the bus, keep the values in case of intentional Reset and send/reset the values through Diag request.
Implemented component which started / stopped EyeqMgr based on Lifecycle and Degradation inputs
Conducted investigations which involved a lot of components: Rte, Diag, Os, BswM, NvM, BAC Components.
Past activities in Yazaki Europe:
Part of Core team
Bug fixing on Dem module
Develop DEM module as per Autosar 4.0 description
Write unit test scripts in python to ensure regression does not happen whenever a functionality is changed
Took over a lot of different components: RamTest, EcuM, Os, Memory stack, WdgM
Investigate startup code, flash module and peripheries for Texas Instruments controller
Past activities in Sii Romania:
Part of Memory team
Develop CDD modules which allowed Memory Stack to connect to Rte via sender receiver interface
Expand Tresos plugins to add new configurations tabs and layers for Cdd's
Bug fixing on Dem/Nvm/Cdd
Implemented restore defaults concept via Diagnostic
Implemented writing on NvM via XCP commands

Current activities in Vehiclevo Gmbh
Part of preanalysis and bugfix team:
Analyzed and fixed multiple issues in Bac components (Adt / Bs / StdDiag / Coding / Prog / Dlog)
Swapped components between core1 and core 2
Implemented StdDiag callout to trigger clearDTC on secondary Memory
Implemented JumpToBoot sequence in BswM
Changed generator to create a new ComIpduGroup
Added Uart logs to debug DoIp / Tcp protocols
Align the state machines of DCM / Dem / StdDiag / NvM in order to fix ClearDTC routine
Analyzed and presented the difference between implementation of WdgM and SftyPfm
Configured WdgM Alive Supervision on multiple cores + investigate whenever a bug was reported for a failed entity
Added Gliwa StopTrigger and markers to be able to have a better overview of the runtime

Tools:
CANoe, Lauterbach Trace32, WinIdea, Elektrobit Tresos Studio, Vector DaVinci, Vector Developer , CVI (Mentor), Fork, Gliwa, Visual Studio , E-SYS, EDIABAS, Wireshark, Carmen, DltViewer, Autosar Builder.

Autosar stack experience:
BswM / EcuM / Memory Stack / Crypto (Bac modules) / DeM / WdgM.