07/19/2025 updated


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FPGA Design Engineer / ASIC Frontend Design Engine
Bangalore, India
India
Masters in VLSI Designft5ttInnovationAutomationCircuit DesignCommunications ProtocolsElectronicsPerl (Programming Language)FirmwareField-Programmable Gate Array (FPGA)Graphic DesignPython (Programming Language)Product DesignShell ScriptSystemVerilogUniversal Asynchronous Receiver/TransmitterVerilog
FPGA ASIC Design Engineer Thank you for visiting my profile. My name is Arpit, a Dedicated Electronics and Firmware Engineer specializing in ASIC/FPGA. Creating Innovative and High Quality Solutions for Electronic Product Development. I also work on Software Dev. Core competencies : - RTL Design for FPGA/ASIC using Verilog and System Verilog. - Automation using Perl Python Shell scripting. - Mixed Signal Circuit design and Layout Design. - Experience on communication protocols as UART, SPI, CAN etc Committed to delivering cost Effecting Solution with prompt communication without compromising performance or deadlines.
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