10/29/2025 updated
100 % available
ASIC Design Verification Engineer specializing in RTL Design and Low-Power Design
RABAT, Morocco
Worldwide
Engineering Degree in Embedded Systems EngineeringC (Programming Language)Advanced Microcontroller Bus ArchitectureArchitecture
ASIC Design and Verification
Advanced expertise in ASIC Flow, RTL Design, Pipeline Design, SoC Design, and Low-Power Design techniques including Clock Gating, Power Gating, and Multi-Vt implementations
Hardware Description Languages and Verification
Proficient in SystemVerilog, Verilog, VHDL, UVM Fundamentals, and comprehensive testbench development with functional coverage analysis
FPGA Development and Synthesis
Extensive experience with FPGA platforms including Xilinx Artix-7, Spartan-3E, Altera DE1, and synthesis tools for timing analysis and design optimization
Programming Languages
Python, Tcl, C, C++, Embedded C, Bash, and Assembly Programming for hardware and software integration
EDA Tools and Simulation
ModelSim, QuestaSim, PowerPro, Vivado, Quartus, Design Compiler, Catapult HLS, and STM32CubeMX for design and verification workflows
Build and Debug Systems
Make, CMake, GDB, and Waveform Debugging for comprehensive development and troubleshooting processes
Communication Protocols
UART, I2C, SPI, CAN, AXI, Avalon, and AMBA protocols for embedded systems integration
Processor Architectures
RISC-V, ARM Cortex-M, and custom processor design with pipeline architecture and hazard detection implementation
Advanced expertise in ASIC Flow, RTL Design, Pipeline Design, SoC Design, and Low-Power Design techniques including Clock Gating, Power Gating, and Multi-Vt implementations
Hardware Description Languages and Verification
Proficient in SystemVerilog, Verilog, VHDL, UVM Fundamentals, and comprehensive testbench development with functional coverage analysis
FPGA Development and Synthesis
Extensive experience with FPGA platforms including Xilinx Artix-7, Spartan-3E, Altera DE1, and synthesis tools for timing analysis and design optimization
Programming Languages
Python, Tcl, C, C++, Embedded C, Bash, and Assembly Programming for hardware and software integration
EDA Tools and Simulation
ModelSim, QuestaSim, PowerPro, Vivado, Quartus, Design Compiler, Catapult HLS, and STM32CubeMX for design and verification workflows
Build and Debug Systems
Make, CMake, GDB, and Waveform Debugging for comprehensive development and troubleshooting processes
Communication Protocols
UART, I2C, SPI, CAN, AXI, Avalon, and AMBA protocols for embedded systems integration
Processor Architectures
RISC-V, ARM Cortex-M, and custom processor design with pipeline architecture and hazard detection implementation
Project history
Developed SPEF Profiler tool to improve VLSI power estimation by integrating post-layout parasitic data into RTL-to-GDS flow. Implemented low-power techniques and created Python/Tcl algorithms for SPEF file parsing and design data analysis. Developed hierarchical name reconciliation achieving 95% net matching accuracy between RTL and physical designs.
Winners of the Orange Summer Challenge 2024, organized by Orange Maroc in partnership with EY, Nokia, and AWS. Developed an innovative IoT solution to assist individuals with speech difficulties. Led hardware development and hard-soft integration, connecting embedded systems with cloud services.