FPGA and Mixed signal ASIC design

Design &Analysis Skills:
Register transfer level (RTL) design, Programmable processor
architectures, Hardware functional verification (PTS anduArchitecture documents), CoReUse IP design. Multi-level
requirements definition, Model based design flows and System
identification/Modeling (Matlab).

Coding &Tools:
VHDL, SystemVerilog for Verification, C++ for Embedded,
Scripting (Matlab, Python 3.5, TCL), Xilinx Vivado, Intel/Altera
Quartus II, Questa & HDL Designer (Mentor Graphics), Genus,
Excelium (Cadence), Matlab/Simulink, Microsoft OS, Linux/Unix
OS.

Core Skills:
Digital micro-architecture extraction (from customer
requirements) and implementation, FIR, FFT, IFFT, QPSK, FSK,
8PSK modulations, HPC Re-conf. architectures, I2C, SPI, CAN
2.0, LIN, DDR protocols, ARM9/FPGA, Xilinx &Altera FPGA,
ESP8266, ESP32, Anadigm FPAA.

Soft Skills:
Analytical and problem solving skills, Result driven, Able to work
autonomously or within a team, Capable to delegate, Striving for
efficiency at work. Work package management(planning and
work coordination).

Configuration Management:
Revision control with SVN, Git, TRAC and JIRA issue
tracking.