02/14/2010 updated
BS
100 % available
VLSI engineer
Sf. Gheorghe, Romania
Worldwide
Dipl.-IngenieurBash ShellPerl (Programming Language)Formal VerificationField-Programmable Gate Array (FPGA)Hardware Description LanguageLithographySimulationsTcl (Programming Language)VerilogVHSIC Hardware Description Language (VHDL)ScriptingApplication Specific Integrated CurcuitsModeling and SimulationProgramming Languages
HDL languages: Verilog, VHDL
Technologies: ASIC, FPGA (Xilinx, Altera)
Simulation Tools: Modelsim, VCS
Synthesis Tools: Synplify, Xilinx ISE, Altera Quartus II, Synopsys
Formal Verification: FormalPro
Scripting: Perl, Tcl, bash
Programming Languages: C, Lex, Yacc
Technologies: ASIC, FPGA (Xilinx, Altera)
Simulation Tools: Modelsim, VCS
Synthesis Tools: Synplify, Xilinx ISE, Altera Quartus II, Synopsys
Formal Verification: FormalPro
Scripting: Perl, Tcl, bash
Programming Languages: C, Lex, Yacc
Languages
GermanGoodEnglishFluentRomanianNative speaker