Keywords
Skills
HDL languages: Verilog, VHDL
Technologies: ASIC, FPGA (Xilinx, Altera)
Simulation Tools: Modelsim, VCS
Synthesis Tools: Synplify, Xilinx ISE, Altera Quartus II, Synopsys
Formal Verification: FormalPro
Scripting: Perl, Tcl, bash
Programming Languages: C, Lex, Yacc
Technologies: ASIC, FPGA (Xilinx, Altera)
Simulation Tools: Modelsim, VCS
Synthesis Tools: Synplify, Xilinx ISE, Altera Quartus II, Synopsys
Formal Verification: FormalPro
Scripting: Perl, Tcl, bash
Programming Languages: C, Lex, Yacc
Project history
Automation, consumer electronics, telecommunications, health-care. More details upon request.
Local Availability
Open to travel worldwide
Only offsite work
