Senior FPGA Development Engineer
Digital Design; Oxford Instruments
Skills
FPGA, Formal Verification, code coverage, coding, Python, debugging, Apollo, UART, SPI, I2S, GPIO, Expander, Verilog, test framework, Xilinx, DOORS, signal processing, data transfer, checksum, Lattice, VHDL, test bench, Tcl, NIOS, 32-bit, C++, JTAG, PCB layout, ASIC, DVB, RTL design-VHDL, simulation, Tcl scripting, assertion, DiseqC, SATA, USB, data analysis, Windows 2000/XP/Vista, Unix, Linux, Sun Solaris, Applications, MS Office viz, Word, Excel, PowerPoint, Access, 8085 and 8086, Programming, C, Scripting Languages, Perl, Lint checker, Spyglass, Simulation tools, VCS, Modelsim, PSPICE, Matlab SimuLink, QuestaSIM, Compiler, DFT Compiler, TAP Controller, BScan, Logic Vision, Clio soft SOS, Git, SVN, Magma's Blast Fusion, Cadence, Avant, Xilinx Vivado, ISE Web pack, Intel/Altera, Quartus-II, Lattice Diamond
Project history
07/2007
-
09/2020
Oxford Instruments, Oxford, England
Responsibilities:
* Concept, Development and Verification of FPGAs
targeting to Drive Technologies - Electric hybrid vehicles
* Hands on expertise in VHDL, Verilog, Functional 13( Post
layout Simulation, Synthesis, P&R and Tcl Scripting for
STA, IP integration, Assertion based test bench
verification
* NIOS-II 32-bit soft core processor implementation and
verification with embedded test software in C++ using
JTAG UART interface
* Delta-Sigma modulators - 5inc3 Filter implementation
* Interaction with Hardware/Software teams for board
bring-up
* Board level verification in mixed signal environment
using oscilloscope and interaction with PCB layout tool
Cadence Allegro
Responsibilities:
* Concept, Development and Verification of FPGAs
targeting to Drive Technologies - Electric hybrid vehicles
* Hands on expertise in VHDL, Verilog, Functional 13( Post
layout Simulation, Synthesis, P&R and Tcl Scripting for
STA, IP integration, Assertion based test bench
verification
* NIOS-II 32-bit soft core processor implementation and
verification with embedded test software in C++ using
JTAG UART interface
* Delta-Sigma modulators - 5inc3 Filter implementation
* Interaction with Hardware/Software teams for board
bring-up
* Board level verification in mixed signal environment
using oscilloscope and interaction with PCB layout tool
Cadence Allegro
09/2017
-
03/2019
FPGA Design / Verification - Digital Design Consultant
Intel
Responsibilities:
* Analysis of Intel Apollo-Lake SoC interfaces and FPGA
hardware preparation
* IP Functional Specification, Implementation and
verification - UART, SPI, I2C and I2S TDM(Audio)
* Bring-up of HW using Mentor layout viewer and
measurements with Oscilloscope
* GPIO Port Expander - SPI Controller Implementation
* Verilog RTL, Test bench, Synthesis, STA, P&R, functional
and timing simulation
* AMBA-AXI bus transactions through FPGA register
control
* Python based test framework to verify Host and Device
transactions
* Early design testing with Xilinx KC705 evaluation
platform
* Analysis of Intel Apollo-Lake SoC interfaces and FPGA
hardware preparation
* IP Functional Specification, Implementation and
verification - UART, SPI, I2C and I2S TDM(Audio)
* Bring-up of HW using Mentor layout viewer and
measurements with Oscilloscope
* GPIO Port Expander - SPI Controller Implementation
* Verilog RTL, Test bench, Synthesis, STA, P&R, functional
and timing simulation
* AMBA-AXI bus transactions through FPGA register
control
* Python based test framework to verify Host and Device
transactions
* Early design testing with Xilinx KC705 evaluation
platform
11/2012
-
05/2017
Digital Design Consultant
FPGA
Bombardier Transportation, London England
Responsibilities:
* Reviewing and analyzing specifications from DOORS
* Cross correlation and Regulator signal processing
* LFSR implementation, data transfer through different
interfaces with checksum
* Experience with ARM Cortex M4 - Flex bus interface
* Writing test models for ADCs, DACs and Flash with SPI
interfaces
* Implementation and Verification of FPGAs - Lattice /
Xilinx
* VHDL, Verilog, Functional Simulation, Lint checking,
Synthesis, Place& Route, post-layout Simulation and
STA with back annotated timing information, test
benches - module / top level and fulfill the requirements
with 100% code coverage
* Board-evaluation for UFM and memory interface
between processor boards using oscilloscope
* Creation of text reports from test bench verification
using assertions
* Documentation - Design and Failure criteria functional
verification test report
* Supporting junior engineers to fix functional, timing and
integration issues
Responsibilities:
* Reviewing and analyzing specifications from DOORS
* Cross correlation and Regulator signal processing
* LFSR implementation, data transfer through different
interfaces with checksum
* Experience with ARM Cortex M4 - Flex bus interface
* Writing test models for ADCs, DACs and Flash with SPI
interfaces
* Implementation and Verification of FPGAs - Lattice /
Xilinx
* VHDL, Verilog, Functional Simulation, Lint checking,
Synthesis, Place& Route, post-layout Simulation and
STA with back annotated timing information, test
benches - module / top level and fulfill the requirements
with 100% code coverage
* Board-evaluation for UFM and memory interface
between processor boards using oscilloscope
* Creation of text reports from test bench verification
using assertions
* Documentation - Design and Failure criteria functional
verification test report
* Supporting junior engineers to fix functional, timing and
integration issues
03/2004
-
05/2007
3nr ASIC Design Engineer
Imagination Technologies
Hertfordshire, England
Responsibilities:
* Development and Verification of demodulator/decoder
DVB-S2 ICs for Set-top box tuner applications
* Translating block level requirements from System C to
VHDL
* Expertise in RTL design-VHDL , simulation, Tcl scripting
for synthesis, STA timing sign-off, DFT scan chain
insertion, formal verification, pre& post layout STA
* Experience in code-coverage 13( assertion based
testbench verification, implementation 13( testing of TAP
controller& Boundary-scan logic, memBIST verification
* System level integration running through synthesis and
STA
* Interaction with IC layout team to solve the timing
issues
* Experience with SPI, I2C, DiseqC, SATA and USB
interfaces
* Prototyping in Xilinx FPGAs
* Project co-ordination with international teams in USA,
France, Belgium and China Showed data analysis in
regular meetings for creating new program
Responsibilities:
* Development and Verification of demodulator/decoder
DVB-S2 ICs for Set-top box tuner applications
* Translating block level requirements from System C to
VHDL
* Expertise in RTL design-VHDL , simulation, Tcl scripting
for synthesis, STA timing sign-off, DFT scan chain
insertion, formal verification, pre& post layout STA
* Experience in code-coverage 13( assertion based
testbench verification, implementation 13( testing of TAP
controller& Boundary-scan logic, memBIST verification
* System level integration running through synthesis and
STA
* Interaction with IC layout team to solve the timing
issues
* Experience with SPI, I2C, DiseqC, SATA and USB
interfaces
* Prototyping in Xilinx FPGAs
* Project co-ordination with international teams in USA,
France, Belgium and China Showed data analysis in
regular meetings for creating new program
Local Availability
Only available in these countries:
Germany
