10/17/2026 updated
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100 % available
Low-level VHDL/FPGA & Embedded Engineer | Fixed-Price
Tucson, USA
Worldwide
About me
Low-level VHDL/FPGA & embedded engineer (C/C++). Original work only — no third-party or open-source code in deliverables. Recent projects: full ULPI fault-injection bridge (187 tests) and dual-MCU USB HID bridge with supervised recovery. Fixed-price on clearly scoped work. Clean, documented source.
Java (Programming Language).NET FrameworkADO.NETTest AutomationC Sharp (Programming Language)C++ (Programming Language)C++/CLIEmbedded SystemsLinux On Embedded SystemsField-Programmable Gate Array (FPGA)Hardware DesignPython (Programming Language)Test DesignUSBVHSIC Hardware Description Language (VHDL)
Low-level digital and embedded engineer focused on VHDL/FPGA design & verification and bare-metal / low-level embedded firmware (C/C++).
I take clean hardware requirements or interface specifications and turn them into reliable, well-structured implementations. Recent original work includes:
- A complete ULPI (USB 2.0) fault-injection bridge in VHDL with packet-level control, occurrence-qualified triggering, CRC mutation, 187 behavioral tests, and synthesis qualification gates
- A dual-MCU USB HID bridge (ESP32-S3) with supervised high-speed UART transport, deterministic health monitoring, staged recovery, and hardware-validated hot-plug behavior
I work across:
- VHDL / FPGA RTL design and verification
- Self-checking testbenches and regression suites
- Protocol and interface logic (USB, UART, SPI, I2C, custom links)
- Embedded C/C++ firmware (bring-up, drivers, reliability/recovery logic, multi-MCU systems)
- Short fixed-scope modules or verification packages
I work fixed-price on clearly scoped deliverables with defined acceptance criteria. I deliver clean, reproducible source with documentation and focus on correct, maintainable low-level results.
Experience
Professional experience0 - 5 years
Freelancer since2026
Languages
EnglishNative speaker
Project history
Designed and implemented a complete ULPI (USB 2.0) fault-injection bridge in VHDL. Included transparent bridging, packet-level corruption/truncation/drop, PID substitution, CRC mutation, occurrence-qualified triggering, control plane, and telemetry. Built hierarchical architecture with freeze-and-wrap discipline across multiple milestones. Developed 187 behavioral tests and synthesis qualification gates. Fully original implementation from specifications — no third-party code.
Designed and implemented a dual ESP32-S3 USB HID bridge with supervised high-speed UART transport, CRC-framed protocol, link health monitoring, heartbeat supervision, and staged recovery (soft / endpoint / root-port). Included peer-loss neutralization and hardware-validated hot-plug behavior. Fully original implementation.