Design & Verification Engg.

India

BE (EC)

India

BE (EC)

Verilog HDL system verilog UVM RTL ASIC FPGA C/C++Perl Scripting FPGA QuestaSim vivado RTL Design Linux

Experienced design verificatin/validation engg. with a demonstrated history of working in the semiconductor industry. Strong enggeniering professional skilled in python, Verilog, System Verilog, Design verification testing, logice design and validation.

Languages

EnglishFluent

Contact form

You need to be logged in to use the contact form.