Electronics and Communications Engineering Student

Technical Skills

I work with C/C++, Python, and MATLAB for hardware simulation, machine learning, and signal processing. My EDA toolset includes Questa Sim, Vivado, Quartus Prime, and Cadence Virtuoso, and I'm fluent in both Arabic and English.

Hardware & RTL Design

I've worked across multiple hardware abstraction levels. I designed a 4-bit ALU in Static CMOS and PTL with a Carry-Lookahead Adder and Barrel Shifter, verified in Cadence Virtuoso, and implemented a WiMax PHY Layer (QPSK channel coding, FEC, interleaving, modulation) with FPGA hardware validation. I modeled the DSP48A1 Xilinx DSP slice in behavioral Verilog, featuring a 5-stage configurable pipeline with cascade chaining and parameterized reset types. I also built a pipelined RV32IC RISC-V processor on a Nexys A7 FPGA, validated against official RISC-V compliance suites.

Machine Learning & Signal Processing

During a research internship at Sabancı University (Summer 2025), I built an FPGA-based RF Modulation Classifier — generating a novel APSK dataset, training a CNN on RadioML 2016.10A, and developing partial hardware acceleration on a RedPitaya FPGA for real-time inference. I also implemented full communication system chains, including AM, PCM, and 16-QAM TX/RX in simulation.

Embedded Systems

I built an autonomous line-following robot using an FSM-based MCU firmware and a bidirectional motor control system with two Arduino boards communicating over Ethernet.

Professional Experience

I interned as a NOC Back Office Engineer at Orange (Summer 2024), working on network architecture, mobile communications, and KPI monitoring. I'm an active IEEE organizing member at AUC and have held HR Head roles in two student associations. I was also a Finalist at the International Science and Engineering Fair (2021).