09/11/2026 updated
100 % available
FPGA & RTL Design Engineer | Xilinx Vivado, Intel Quartus, SystemVerilog
Myjava, Slovakia
Only remote
Doctor of Philosophy (PhD) in Electrical and Electronics EngineeringAbout me
FPGA design engineer (PhD) with 12+ years in digital & mixed-signal IC design. Hands-on: Xilinx Zynq UltraScale+ & Intel Agilex, Vivado/Quartus, RTL (SystemVerilog), timing closure, CDC, PetaLinux. Background: CPU/AI-accelerator RTL. B2B contracts, remote-first, based in Slovakia (CET).
C (Programming Language)Pcb Layout
FPGA Design & Implementation
Hands-on FPGA project experience on Xilinx Zynq UltraScale+ MPSoC and Intel Agilex platforms, including Vivado and Quartus tool flows, peripheral hub design, clock tree architecture, timing closure, and CDC analysis.
RTL/ASIC Design & Verification
Over 6 years of RTL/ASIC design experience covering CPU and AI-accelerator RTL, logic synthesis, SoC/IP integration, RTL verification using Verilog/SystemVerilog testbenches, and self-checking test cases in ModelSim.
Mixed-Signal IC Design & Layout
Over 6 years in mixed-signal IC design, including full custom layout, floor-planning, mask set generation (GDS-II), and design of high-performance power devices such as LDOs and SmartFETs for the automotive sector.
SoC/IP Integration
Definition and management of communication protocols and interfaces between subsystems, including integration of high-speed IP cores and HW/SW co-design cycles in multiprocessor SoC environments.
AI & Machine Learning Acceleration
RTL design of AI training and inference units supporting multiple data formats (INT, FP32, FP16, BF16, FP8, FP4), and development of high-performance speech separation algorithms using custom Neural Network architectures.
Digital Signal Processing (DSP)
PhD research in speech-signal processing with deep DSP expertise, including mathematical modeling in MATLAB and Python for real-time signal processing applications.
Cryptography & Hardware Security
Optimization and implementation of high-throughput cryptographic modules (AES, SHA) for secure data processing within RTL designs.
Embedded Linux & PetaLinux
Management of full HW/SW co-design cycles including Vivado block design, bitstream generation, and PetaLinux OS integration on embedded platforms.
Python/C/C++ Programming
Programming skills in Python, C, and C++ applied to hardware validation, signal processing modeling, and data science tasks including deep learning and computer vision.
PCB Design & Hardware Validation
PCB design, oscilloscope-based debugging, and hardware bring-up and validation during prototyping of new products.
Hands-on FPGA project experience on Xilinx Zynq UltraScale+ MPSoC and Intel Agilex platforms, including Vivado and Quartus tool flows, peripheral hub design, clock tree architecture, timing closure, and CDC analysis.
RTL/ASIC Design & Verification
Over 6 years of RTL/ASIC design experience covering CPU and AI-accelerator RTL, logic synthesis, SoC/IP integration, RTL verification using Verilog/SystemVerilog testbenches, and self-checking test cases in ModelSim.
Mixed-Signal IC Design & Layout
Over 6 years in mixed-signal IC design, including full custom layout, floor-planning, mask set generation (GDS-II), and design of high-performance power devices such as LDOs and SmartFETs for the automotive sector.
SoC/IP Integration
Definition and management of communication protocols and interfaces between subsystems, including integration of high-speed IP cores and HW/SW co-design cycles in multiprocessor SoC environments.
AI & Machine Learning Acceleration
RTL design of AI training and inference units supporting multiple data formats (INT, FP32, FP16, BF16, FP8, FP4), and development of high-performance speech separation algorithms using custom Neural Network architectures.
Digital Signal Processing (DSP)
PhD research in speech-signal processing with deep DSP expertise, including mathematical modeling in MATLAB and Python for real-time signal processing applications.
Cryptography & Hardware Security
Optimization and implementation of high-throughput cryptographic modules (AES, SHA) for secure data processing within RTL designs.
Embedded Linux & PetaLinux
Management of full HW/SW co-design cycles including Vivado block design, bitstream generation, and PetaLinux OS integration on embedded platforms.
Python/C/C++ Programming
Programming skills in Python, C, and C++ applied to hardware validation, signal processing modeling, and data science tasks including deep learning and computer vision.
PCB Design & Hardware Validation
PCB design, oscilloscope-based debugging, and hardware bring-up and validation during prototyping of new products.
Experience
Professional experience0 - 5 years
Freelancer since2025
Languages
GermanBasic knowledgeEnglishFluent
Project history
Designed and implemented a custom Peripheral Hub on Xilinx Zynq UltraScale+ MPSoC integrating high-speed IP cores. Designed and optimized PLL-based clock architectures and resolved timing closure challenges including CDC hazards. Wrote Verilog/SystemVerilog testbenches in ModelSim. Managed full HW/SW co-design cycle with Vivado and PetaLinux. Integrated Intel Clocked Video IPs with F-Tile HDMI 2.1 transceivers for 4K/8K video processing on Intel Agilex.
Owned the full RTL architecture and design of the Vector Unit within a high-performance CPU. Defined and managed communication protocols and interfaces between the Vector Unit, Instruction Scheduler, and Data Cache. Led the RTL design of AI training/inference units supporting multiple data formats (INT, FP32, FP16, BF16, FP8, FP4).
Designed and implemented micro-architecture for specialized execution modules with lint-clean RTL and synthesis closure. Developed high-performance MAC units and optimized critical timing paths. Optimized and implemented high-throughput cryptographic modules (AES, SHA). Built unit-level test cases and self-checking Verilog/SystemVerilog test benches to verify RTL functionality.