09/18/2023 updated
60 % partially available
FPGA/Embedded Engineer | SystemVerilog, VHDL, SpinalHDL
Gliwice, Poland
Only remote
BSc Electronics and TelecommunicationAutomationDevOpsEmbedded SystemsFirmwareField-Programmable Gate Array (FPGA)Space ExplorationSystemVerilogVHSIC Hardware Description Language (VHDL)Tooling Assembly and DismantlingDocker
Embedded developer by day, DevOps engineer by night.
I strive to create high-quality, well-tested and documented solutions in established technologies while actively exploring the new and shiny. For tooling, automation, Docker and CI, I'm your man.
I feel the best in complex projects requiring both system-level and in-detail perspectives, connecting multiple domains from hardware through gateware and firmware up to the software running in the cloud. There's nothing better than a perfectly integrated project delivered on time that serves the client's needs.
In my spare time, I like to play tennis. I also have lots of 3D printing experience, which I gladly share, and a deep interest in space exploration and cutting-edge technologies.
I strive to create high-quality, well-tested and documented solutions in established technologies while actively exploring the new and shiny. For tooling, automation, Docker and CI, I'm your man.
I feel the best in complex projects requiring both system-level and in-detail perspectives, connecting multiple domains from hardware through gateware and firmware up to the software running in the cloud. There's nothing better than a perfectly integrated project delivered on time that serves the client's needs.
In my spare time, I like to play tennis. I also have lots of 3D printing experience, which I gladly share, and a deep interest in space exploration and cutting-edge technologies.
Experience
Professional experience5 - 10 years
Freelancer since2022
Languages
GermanGoodEnglishFluentPolishNative speaker
Project history
System and kernel development: porting Tizen OS to RISC-V and Linux driver development for Android.System
Part of a team developing a transparent WireGuard smart NIC achieving speeds up to 100Gbps. Project implemented on Xilinx/AMD Alveo U50 FPGA acceleator (100G Ethernet + PCI-E) with RISC-V soft core.
My main focus was on the Scalable Pipelined Lookup IP core providing fixed-latency IP address lookup.
Skills: RISC-V · FPGA · C · SystemVerilog · Git · Xilinx Vivado · Linux · Python · SpinalHDLSkills
My main focus was on the Scalable Pipelined Lookup IP core providing fixed-latency IP address lookup.
Skills: RISC-V · FPGA · C · SystemVerilog · Git · Xilinx Vivado · Linux · Python · SpinalHDLSkills
Lead embedded Linux and SpinalHDL FPGA engineer in a project involving acquisition of 360° in-orbit images, video pipeline scheduling, and interfacing with a satellite communication module. Development of testbenches, functional tests, the Linux driver for the camera, system architecture and CI. Involved in communication with the client.
Embedded Linux and VHDL FPGA developer in a design for high-speed industrial/medical X-ray imaging equipment with 10G Ethernet.
Embedded Linux and VHDL FPGA developer in a design for high-speed industrial/medical X-ray imaging equipment with 10G Ethernet.