05/15/2026 updated
100 % available
FPGA Lead Design Engineer | Embedded Systems & Firmware Design
Stafford, United Kingdom
Only remote
BEng Electronics, National University of Science and Technology (CGPA 3.41/4.00)Hardware DesignMATLABSystems DesignSystemVerilogVerilogFpga HardwareVHDL Programming
FPGA Design & HDL Programming
Over 12 years of experience in FPGA design using Verilog HDL and VHDL on toolchains including Microsemi (IGLOO2, ProASIC), Xilinx (ISE, XST, Vivado), and Altera. Design and implementation of firmware architectures for complex embedded systems in aerospace, energy, and defence sectors.
MATLAB Simulink Model-Based Design
Extensive application of MATLAB Simulink for model-based design in safety-critical projects, including automated next-generation hardware designs for aerospace (Airbus A350, HAWK YDC) and industrial valve control systems. Trained in MATLAB Basic, Model-Based Simulink, System Composer, and Code Generation.
Embedded Systems & Firmware Development
Deep expertise in embedded systems development using C, including device driver creation, communication protocol implementation (SPI, I2C, UART, CANBUS, SerDes, Ethernet), and firmware design for microcontrollers and FPGAs across aerospace, satellite, and industrial applications.
ASIC Design Tools
Practical experience with Synopsis and Cadence ASIC design tools, as well as ModelSim, QuestaSim, and Multisim for simulation and verification of digital designs.
Communication Protocols
Implementation and testing of various communication protocols including 1Gb PON (SerDes), 1G Ethernet, UART, I2C, SPI, CANBUS, and RS232/RS485 in both FPGA and embedded environments.
Verification & Validation
Experience with NI TestStand, NI Veristand, UVM methodology, and System Verilog for verification and validation of hardware and firmware designs, including MIL and HIP testing.
Agile Project Management & Version Control
Proficiency in agile methodologies (Scrum and Kanban) and version control tools including Jira, Confluence, Git, SVN, Smartsheet, and Polarion ALM.
RTL Design & Optimisation
Development and optimisation of RTL designs for high-speed data processing, achieving significant reductions in latency and improvements in system performance, including NAND Flash model and controller development in System Verilog.
Airborne Standards & Safety-Critical Design
Knowledge and application of DO-254, D0178 Airborne Standards, ESA (ECSS-E-70) standards, and FMEA for fault finding in safety-critical aerospace and satellite systems.
PLC & System Engineering
Understanding of PLC, C++, Cadence, and system engineering practices, with over 1 year of experience as a system engineer on satellite TT&C communication systems.
Over 12 years of experience in FPGA design using Verilog HDL and VHDL on toolchains including Microsemi (IGLOO2, ProASIC), Xilinx (ISE, XST, Vivado), and Altera. Design and implementation of firmware architectures for complex embedded systems in aerospace, energy, and defence sectors.
MATLAB Simulink Model-Based Design
Extensive application of MATLAB Simulink for model-based design in safety-critical projects, including automated next-generation hardware designs for aerospace (Airbus A350, HAWK YDC) and industrial valve control systems. Trained in MATLAB Basic, Model-Based Simulink, System Composer, and Code Generation.
Embedded Systems & Firmware Development
Deep expertise in embedded systems development using C, including device driver creation, communication protocol implementation (SPI, I2C, UART, CANBUS, SerDes, Ethernet), and firmware design for microcontrollers and FPGAs across aerospace, satellite, and industrial applications.
ASIC Design Tools
Practical experience with Synopsis and Cadence ASIC design tools, as well as ModelSim, QuestaSim, and Multisim for simulation and verification of digital designs.
Communication Protocols
Implementation and testing of various communication protocols including 1Gb PON (SerDes), 1G Ethernet, UART, I2C, SPI, CANBUS, and RS232/RS485 in both FPGA and embedded environments.
Verification & Validation
Experience with NI TestStand, NI Veristand, UVM methodology, and System Verilog for verification and validation of hardware and firmware designs, including MIL and HIP testing.
Agile Project Management & Version Control
Proficiency in agile methodologies (Scrum and Kanban) and version control tools including Jira, Confluence, Git, SVN, Smartsheet, and Polarion ALM.
RTL Design & Optimisation
Development and optimisation of RTL designs for high-speed data processing, achieving significant reductions in latency and improvements in system performance, including NAND Flash model and controller development in System Verilog.
Airborne Standards & Safety-Critical Design
Knowledge and application of DO-254, D0178 Airborne Standards, ESA (ECSS-E-70) standards, and FMEA for fault finding in safety-critical aerospace and satellite systems.
PLC & System Engineering
Understanding of PLC, C++, Cadence, and system engineering practices, with over 1 year of experience as a system engineer on satellite TT&C communication systems.
Project history
Working on Airbus A350 Spoiler, HAWK YDC, Marcia, Model and SoC Development and Requirements Management. Automated Next Generation HWAK YDC using VHDL and MATLAB Simulink Model Base Design using Microsemi toolchain (IGLOO2). Overseeing development activities including coding, synthesizing, troubleshooting, and design completion into factory using DO-254, D0178 Airborne Standards and Common Firmware Block with Commons Software Block Libraries. Additional project: 2.5 Gb PHY loopback Test using Arria 10 and Cyclone 10 Development Kit in Verilog for Ion Bus architecture.
Sub Module (GEN 2 Gate Control Card PCB 2300) NPI Model and SoC Development and Verification. Industrialized Next Generation Valve Submodule using Verilog and MATLAB Simulink Model Base Design using Microsemi toolchain (IGLOO2) including 1Gb PON (SerDes) Interface, 10Ksps SPI ADC Communications plus I2C interface. Led development activities including coding, synthesizing, troubleshooting, design reviews, MIL and HIP testing. Coordinated cross-functional teams for successful product launch. Delivered Next Generation Gate Unit Control Card Firmware for HVDC Project.
Series 5 and 6 Valve Base Electronics and Sub Module (GEN 1 Gate Control Card PCB 2266/2278 plus GEN1+ Full Bridge) SoC Development and Verification. Designed and developed firmware architecture using Verilog and VHDL on Microsemi toolchain (IGLOO2 and ProASIC). Supported verification and validation tools using Verilog on Intel toolchain (Arria II GX). Implemented communication protocols including 1Gb PON (SERDES), 1G Ethernet, UART, I2C, SPI. Migrated series 5 VBE firmware from Altera 13.1sp to Xilinx Vivado 2016.4 on Vertex 7. Delivered Next Generation Series 6 VBE firmware architecture and Gate Unit Control Card Firmware for STATCOM and HVDC Project.