09/28/2026 updated
100 % available
Freelance Senior IC Layout Engineer & Physical Design Leader | RF, Analog & Mixed Signal
Handen, Sweden
Only remote
About me
Freelance IC layout lead with 25+ years in analog, RF and mixed-signal. I take chips from floorplan to tape-out on 22, 14, 12 and 7 nm FinFET, including RF and mmWave blocks at 100 GHz and above. Based in Stockholm, working through my own company
High FrequencyRadio Frequency
CORE EXPERTISE
Full-custom IC layout for analog, RF, mmWave, mixed-signal, NVM and IP blocks, from block level to full chip and tape-out.
RF AND HIGH-SPEED
RF and mmWave layout on the highest-frequency blocks (100 GHz and above), plus high-speed analog and mixed-signal blocks: RF demux, ADCs, DACs, LNAs, PLLs, PAs, VCOs. Precision device matching, transmission lines, crosstalk control, substrate isolation and parasitic control.
CHIP LEVEL
Full-chip floorplanning, top-level assembly, sub-block integration, pad ring, ESD protection, multiple voltage domains, power routing, IR drop, electromigration, latch-up, WPE, LOD and DFM.
PROCESS NODES AND FOUNDRIES
22 nm, 14 nm, 12 nm and 7 nm FinFET and CMOS, plus 28 nm and older nodes. Foundry experience with TSMC, GlobalFoundries, STMicroelectronics and UMC.
TAPE-OUT AND LEADERSHIP
Foundry interface, tape-out checks, PCM test structures, mask and reticle data, MPWs. Layout planning, resource budgeting, flow and methodology, training of junior engineers, coordination with design, CAD, process, lithography and packaging teams.
TOOLS AND SCRIPTING
Cadence Virtuoso XL, Siemens Calibre (DRC, LVS, DFM, ERC, ANT), PVS, Assura. SKILL scripting, Shell, Sed, Awk, Verilog. DesignSync and SVN.
PRODUCTS
Baseband, mobile terminal, optical networking, automotive, smart card, NFC and RFID.
Experience
Professional experience10+ years
Freelancer since2016
Languages
EnglishFluentFrenchNative speaker
Project history
Drive full-custom layout, floorplanning, and physical verification for high-complexity silicon projects across telecommunications, mobile terminals, baseband units, and optical networking applications. Manage end-to-end physical design workflows from initial block sizing to final tape-out mask preparation. Direct top-level chip assembly, pad ring creation, ESD protection placement, and core power distribution routing. Design and optimize critical high-frequency exceeding 100 GHz and analog blocks including ADCs, DACs, PLLs, and RF Demux circuits in advance nodes. Execute rigorous physical verification to mitigate IR drop, electromigration, crosstalk, and latch-up risks. DRC/LVS closure and yield optimization.
Block level and top-level full-custom layout analog, RF, NVM and IP blocks from scratch to tape out. Project and team management. Layout activities responsible including tape-out, flow and methodologies.
Senior Tape Out / Mask Layout Designer / Reticle Design Engineer.