Senior Principal ASIC Specialist Consultant

5G LTE direct mode transmitter verification:


* tx-top-level verification strategy
* create register layer UVM testbench with cycle and bit accurate verification towards c++ reference,
* constraint random verification to achieve coverage goals functional and code coverage
* setup Jenkins in Leuven site for continous integration
* setup vManager for regression
* top level integration
* gate level simulations




MIPI Front end module verification:


* Create UVM testbench to support new features
* setup vManager for regression
* gate level simulations



Define next digital architecture
* Support of LO/2 to give better spectral performance compared with LO/3
* Re-architect clock tree
* Re-architect digital processing up-sampling chain to reduce power by approximately 50%
* HLS synthesis of DPD module
* Formal verification of IP blocks

Architectural specification of an ARM Cortex M3 mixed signal SOC for a lithium battery charger
:
Development of the target IC Specification
Development of the mixed signal architecture design specification
IP selection - peripherals, bus interconnection, NVM, SRAM, standard cell IP selection
Maintain area/power excel spread sheet Defining analogue and digital interfaces
top-level verification strategy
Timescales, costing and risks the development
Outline of DFT test strategy

Architectural definition and digital technical lead of NFC powered smart card mixed signal SOC
with Cadence BBE16EP DSP:
Requirement management with customer
Development of the architecture design specification, optimise memory architecture Define
clock gating strategy
Illustrate potential benefits of using DVFS techniques on total power
Generate and maintain full list if IP requirements, including vendor options where available,
Setup NDA
IP selection - peripherals, bus interconnection, NVM, SRAM, standard cell IP selection
Maintain area/power excel spread sheet
Risk management of the development
Outline of DFT test strategy
Technical lead of digital development
Clock, reset and power management implementation
Cadence BBE16EP connectivity and integration
Top level integration
Setup Jenkins for continuous integration FPGA
prototyping

Sensium Healthcare develops wireless solutions, offering is SensiumVitals®, a wireless system
for measuring the vital signs of patients in general wards and A&E departments.


Wireless ARC based SOC RTL development inclusing WBAN 802.15.6 development, PMU, clock
distribution, AES CCM, security engine, NSP legacy low power wireless protocol, dedicated low
power heart rate hardware accelerator, SRAM arbitration, APB / ADC and RF interfaces.


Development of corresponding block level UVM register layer verification against reference
models. Setting up Jenkins regression environment including Python scripting development.


Setting up Synopsys and Cadence synthesis and power compiler flow.

Frontier Microsystems employees (the silicon team) are at risk of redundancy following the
decision of the Board to close Frontier Microsystems, after TSC's funding to acquire Frontier
microsystems fell through. All ASIC development has been put on hold for now.