Embedded Systems Consultant, FPGA cryptocurrency miner, Linux BSP

Implemented Wireguard VPN protocol in FPGA for 100 Gbit/s SmartNIC on AMD
Alveo U50. Architect and lead small team, code implementation. Vivado SpinalHDL,
SystemVerilog, C, Rust, VexRiscv, RISC-V, Verilator, GHDL, CocoTB, SpinalSim, CI/CD.

Helped approx. 70 high-tech companies. Define CPU, SoC, GPU, FPGA system architectures
(COTS/custom hardware, RTL firmware, open-source, proprietary software), make
trade-offs, select hardware components, open-source software, implement board support
software, FPGA firmware, kernel ports, device drivers, middleware and applications. I
work remotely in own office and lab spaces, fixed price or on hourly tarif.
Core technologies
C, SystemVerilog, Linux, AMD and Intel FPGA and MPSoC, Yocto, OpenEmbedded,
ARM, RISC-V, x86, PowerPC, PCI Express, Ultrascale+, GCC, GDB, U-Boot, SpinalHDL

Developed own products portfolio
Come up with, design, develop, sell and provide intellectual property and support.
* Lancero PCI Express SGDMA PCIe for Intel FPGA
which is the background technology for Amazon AWS ECS F1 FPGA acceleration.
* JPEG-LS Lossless image compressor for AMD/Intel FPGA's,
* i.MX53/Cyclone V industrial camera reference design.




Customers
Some of my direct customers include Cymer/USA, ASML/Netherlands, Robert Bosch
Car Multimedia GmbH/Germany, Philips Innovation Services/Netherlands, National
Institute of Standards and Technology/USA, Hexagon and Leica Geosystems AG/Switzerland,
Unitron/Netherlands, ASML/Netherlands, Pentacom/Germany, Newtec/Germany,
CineFlow/Canada, Xilinx/USA, TÜV/Netherlands.

Professional Experience, Self-Employed

A summary of my portfolio (incomplete due to non-disclosure agreements):

Create and provide a three-day on-site customer training at Hensoldt Optronics GmBH,
to learn their software teams to develop Linux device drivers for Xilinx Zynq designs.