Skills
• Test plan definition for Complex SOC modem.
• Manufacturing test mode verification using vhdl test bench environment.
• Scan chain insertion using DFTMAX .
• Scan test mode verification using Tetramax tool of Synopsys.
• Scan pattern simulation using stildpv.
• Architecture & Design compensation cell Built In Self-Test engine in 65nm with vhdl.
• Functional verification of complex blocs: Digrf, DLL, PLL, DDR interface, JTAG.
• Memory bist test.
• Old life test patterns development.
Project history
Work experience:
- oct 2006 -august 2008: dft engineer at stmicroelectronics
- August 2008-july 2013 senior dft engineer at stericsson
Local Availability
Only available in these countries:
Morocco
