12/06/2023 updated

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Analog and Mixed signal layout design Engineer, Analog Layout Design Engineer

Ireland
Worldwide
B.Tech (ECE) & PG DIPLOMA IN VLSI DESIGN
Ireland
Worldwide
B.Tech (ECE) & PG DIPLOMA IN VLSI DESIGN

Profile attachments

RESUME_AMS.pdf

Computer-Aided DesignElectronic Design AutomationFloor PlanningGraphic DesignRoutingCadence VirtuosoLinux Virtual ServerBeta TestingGenesysVlsi DesignPhysical VerificationMixed Signal CircuitsData Generation
beta release, Cadence, Virtuoso, CAD, file generation, EDA tools, genesys, LVS, Physical Verification, routing, VLSI Design , DRC, LVS, EMIR ,FLOORPLAN ,

Experience

Professional experience5 - 10 years
Freelancer since2023

Languages

EnglishFluent

Project history

SENIOR DESIGN ENGINEER

INTEL

Other

1000-5000 team member

• PDK Kit Development (alpha and beta release).
• IPQA – Regression comparison of on different opts with multiple runset and multiple KIT_ITER.
• RVQA – Regression comparison with pre-layout and post-layout frequency with change/update in runset, opts, KIT_ITER .
• FLOWS :: Megatest flow , RC Comparison, ISOTOPE, PORTS, Instances, Multiple corners, PEAC flow , RV , standalone .
• Raise HSD queries and validating the results/experiments.
• Description/Responsibilities: Validate the PDK contents such as Pcells, models, PVdecks, techfiles, EDA tools (Cadence ), create test cases, DRC, LVS, Build & run quality checks,
• Created some basic schematic and layout test cases to verify DRC, LVS and extraction & QRCverification tools.

Analog and Mixed signal layout design Engineer

Altran technologies pvt ltd; Sankalp semiconductor (An HCL ltd)

Analog Layout Design Engineer

Arise Technosolutions

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