11/09/2026 updated
JS
partially available
info: Available evenings and weekends
Principal Layout Engineer - Semiconductor Analog / RF Layout Design
South Korea
Only remote
Bachelor of Science in Electronics EngineeringAbout me
Senior Analog/RF IC Layout Engineer with 20+ years of experience in full-custom layout, mixed-signal ICs, and chip-top integration. Skilled in Cadence Virtuoso, Calibre DRC/LVS, matching, guard rings, PDK-based layout, and SKILL/Python automation. Based in South Korea, seeking remote projects.
Analog & RF Front-End Layout Design
Expertise in analog and RF front-end (RFFE) layout including chip top integration, sub-block layout, power and ground network planning, and noise-free floorplanning with shielding. Extensive experience with LDO, OSC, IO, power clamp, charge pump, level shifter, bump pad decoder, and various analog sub-blocks across multiple technology nodes.
Semiconductor Layout Area Minimization
Consistent track record of die-size and mask-layer reduction proposals adopted for cost savings. Proven ability to identify and implement methods to reduce the number of mask layers and die size across multiple projects and foundry processes.
EDA Tools & Layout Automation
Proficiency in Cadence 6.1.7/8, Calibre (DRC, LVS, PEX, FXOR) 2022 ver., PVS (DRC, LVS), Virtuoso-XL, and PnR tool (Encounter). Development and deployment of 10+ custom Skill scripts and an automatic dummy-fill script for in-house layout workflows.
Chip Top Floorplanning & Integration
Extensive experience in chip top layout integrating RF, analog, digital, and bump pad components (Cu pillar and solder bump types). Skilled in power and ground route planning, top floorplan design, and wire-bonding and WLCSP packaging integration.
Foundry Process Knowledge
Broad experience across bulk CMOS and SOI processes from 500nm down to 28nm, including eFlash, EEPROM, SRAM, and e-fuse options. Foundries include HHGrace, Key Foundry, Samsung, TSMC, Global Foundries, and Tower.
Digital PnR Guideline Development
Creation and documentation of digital PnR guidelines covering pin location, power and ground route guides, and block placement for PnR engineers across multiple chip projects.
ESD & Noise Design
Design and verification of ESD protection meeting HBM (over 2kV) and CDM (1kV) standards. Efficiency floorplanning for noise-free design with shielding applied across multiple RF front-end projects.
Team Leadership & Project Management
Experience as project leader and layout team lead/manager, guiding junior, LNA, and controller layout engineers. Proposed methods for efficient project management using Cadence Library Manager.
Packaging Development
Background in PKG development including wire bonding, molding, solder ball mount, singulation, and EVI. Experience with DOE of Cu-pillar bump (40k-50k dies) and preparation of PKG documents including wire bonding spec and laser marking spec.
Analog IC Design & Simulation
Hands-on experience in touch sensor IC analog design, layout, and simulation covering DAC, bandgap reference, ring oscillator, sense block, ROM, and EEPROM blocks across multiple channel configurations (1CH to 20CH).
Expertise in analog and RF front-end (RFFE) layout including chip top integration, sub-block layout, power and ground network planning, and noise-free floorplanning with shielding. Extensive experience with LDO, OSC, IO, power clamp, charge pump, level shifter, bump pad decoder, and various analog sub-blocks across multiple technology nodes.
Semiconductor Layout Area Minimization
Consistent track record of die-size and mask-layer reduction proposals adopted for cost savings. Proven ability to identify and implement methods to reduce the number of mask layers and die size across multiple projects and foundry processes.
EDA Tools & Layout Automation
Proficiency in Cadence 6.1.7/8, Calibre (DRC, LVS, PEX, FXOR) 2022 ver., PVS (DRC, LVS), Virtuoso-XL, and PnR tool (Encounter). Development and deployment of 10+ custom Skill scripts and an automatic dummy-fill script for in-house layout workflows.
Chip Top Floorplanning & Integration
Extensive experience in chip top layout integrating RF, analog, digital, and bump pad components (Cu pillar and solder bump types). Skilled in power and ground route planning, top floorplan design, and wire-bonding and WLCSP packaging integration.
Foundry Process Knowledge
Broad experience across bulk CMOS and SOI processes from 500nm down to 28nm, including eFlash, EEPROM, SRAM, and e-fuse options. Foundries include HHGrace, Key Foundry, Samsung, TSMC, Global Foundries, and Tower.
Digital PnR Guideline Development
Creation and documentation of digital PnR guidelines covering pin location, power and ground route guides, and block placement for PnR engineers across multiple chip projects.
ESD & Noise Design
Design and verification of ESD protection meeting HBM (over 2kV) and CDM (1kV) standards. Efficiency floorplanning for noise-free design with shielding applied across multiple RF front-end projects.
Team Leadership & Project Management
Experience as project leader and layout team lead/manager, guiding junior, LNA, and controller layout engineers. Proposed methods for efficient project management using Cadence Library Manager.
Packaging Development
Background in PKG development including wire bonding, molding, solder ball mount, singulation, and EVI. Experience with DOE of Cu-pillar bump (40k-50k dies) and preparation of PKG documents including wire bonding spec and laser marking spec.
Analog IC Design & Simulation
Hands-on experience in touch sensor IC analog design, layout, and simulation covering DAC, bandgap reference, ring oscillator, sense block, ROM, and EEPROM blocks across multiple channel configurations (1CH to 20CH).
Languages
EnglishFluentKoreanNative speaker
Project history
Project Leader of the mobile layout team. Responsible for Healthcare MCU chip top and sub-block layout (DIG: SRAM + eFlash, ANA: SDADC, PLL, LDO, OSC), mobile eOIS chip top and sub-block layout (1.8V-3.3V and 1.8V-5.5V variants), GPIO layout (I2C and I3C), SD ADC and SAR ADC 15-bit layout, layout area minimization, FIB report analysis, and Skill automation with 10+ custom scripts.
Layout engineer lead guiding LNA and controller layout engineers. RF front-end switch design for China and S phones and tablets (OMH FEMiD, MIMO LFEM, LB PAMiD, n77 PAMiF, LFEM, WiFi FEM, automotive RFFE). Analog sub-block and chip top layout, noise-free floorplanning, ESD design, digital PnR guideline, mask layer and die size reduction, layout area minimization, FIB report analysis. Tape-out record: 2021-2024 with up to 300 designs per run. Mass production for phones and tablets.
RFFE modules for China, S and A phones (OMH, FEM, PAMiD). Analog sub-block layout for SW and controller design teams. Chip top layout (RF + analog + digital + bump pad, Cu pillar only). DOE of Cu-pillar bump (40k-50k dies). Noise-free floorplanning, ESD design, digital PnR guideline, dummy-fill automation script, automated place-and-route (Innovus), die size and mask layer reduction, layout area minimization, FIB report analysis. Tape-out record: 2015-2021 with up to 3,000 designs per run. Mass production successfully initiated.