12/16/2025 updated

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QA Automation Engineer

Yerevan, Armenia
Worldwide
Master degree in Electronic Design Automation.
Yerevan, Armenia
Worldwide
Master degree in Electronic Design Automation.

Profile attachments

RazmikAlverdyanCV.pdf

About me

Web / Mobile QA Automation engineer with background in electrical engineering, IC design automation.

Computer-Aided DesignMicrosoft WindowsAdobe AcrobatAnalogue ElectronicsVery-Large-Scale IntegrationElectrical EngineeringAtlassian JiraAutomationBash ShellUnixC++ (Programming Language)DatabasesDebuggingLinuxIntegrated Circuit DesignDigital IntegrationElectronic Design AutomationElectromagnetismElectronic MailingPerl (Programming Language)SemiconductorFailure Mode Effects AnalysisField-Programmable Gate Array (FPGA)Revision Control SystemsWeb BrowsersIntegrated CircuitsIntellectual PropertiesPython (Programming Language)Unix ShellLithographyLynxMaintenanceMicrosoft OfficePascal (Programming Language)PerforceQuality ManagementResearch and DevelopmentRelease EngineeringCadence VirtuosoShell ScriptSimulationsStandardizationSubversionTcl (Programming Language)Test CaseTest PlanningTortoiseSVNUSBLinux Virtual ServerVivadoScriptingApache OpenOfficeComplementary Metal-Oxide Semiconductor (CMOS)Application Specific Integrated CurcuitsInformation TechnologyVlsi DesignPhysical VerificationOperational SystemsMentor GraphicsMixed Signal CircuitsPhysical DesignSoftware Version ControlProgramming Languages
Experience
QA Department: Software Engineer at Instigate CJSC, Armenia:  Apr/11/2016 – Aug/01/2016
Tools QA:
  • EDA tool QA,
  • Test plan / test case development using Python
  • Regression run for developed test cases,
  • Bugs debug, fixed bug validation,
  • Xilinx FPGA design and verification flow, Vivado Design Suite overview


Staff PDK Development Engineer at Symmid Corporation ( Altis Semiconductor ): February 2014 - February 2016
130NM RF, High-Voltage, Low-Power PDK development and support for Altis Semiconductors: . Calibre
code development and support, . Cadence Physical Verification System (PVS) code development and
support, . Physical Verification (PV) QA, testcase generation, QA flow support / automation, . SKILL
PCell development, QA, integration in PDK and support, . Application Extension Language (AEL) PCell
development, QA and support, . PCell development QA flow support, testcase generation automation,
Momentum EM simulation flow support, . Momentum EM simulation of inductor PCell, database generation for inductor finder tool


R&D Engineer, Sr I at Synopsys Armenia CJSC: Feb 2005 - February 2014
Work on Hard IPs release related activities. Work on Hard IPs Release flow improvement / automation. Work
on Mixed-Signal Intellectual Property (MSIP) standardization. Initiation/participation in the discussions
to update/improve Hard IPs development and release checklists to meet latest development and customer
requirements. Work with RnD and CAD teams to improve quality of deliverables submitted to release team,
make suggestion for automating generation of views.

• Maintenance and support of Synopsys EDA tools such us (Cosmos, CustomDesigner, Hercules, Star-RCX,
etc.). • Development and maintenance of CustomDesigner PDK, • Development and support of DRC/LVS/
PEX decks and CosmosLE/CustomDesigner. • Development of scripts in Linux environment: PERL, TCL,
shell languages. Automation of everyday common tasks. • Development, setup and support of automated IC
design and verification environment for following types of projects (USB2 PHY, HSIC PHY, PICO PHY,
USB3 PHY, IO LIBRARY, SC LIBRARY, DDR). Includes netlist generation, IC physical verification,
database automated analysis and modification.

Skills & Expertise
TCL, EDA, Perl, Physical Verification, Linux, Shell Scripting, IC, Integrated Circuit Design, DRC, VLSI, Mixed Signal, LVS, Scripting, Unix Shell Scripting, ASIC, Physical Design, Unix, CMOS, C++, Csh, Analog Circuit Design, Perforce, Hercules, Release Engineering, Cadence Virtuoso, Cadence Skill, Calibre, Version Control Tools, Cadence Virtuoso Layout Editor, Cadence Virtuoso XL, Tortoise SVN, Subversion, Electromagnetic Simulation, Inductors, Synopsys Lynx Design System, FMEA, ISO, Cadence Physical Verification System (PVS), Agilent ADS, Momentum (EM simulator), Application Extension Language (AEL), Cadence, Semiconductors

Summary of qualifications:
  • Semiconductor Technologies: TSMC40-180nm, UMC45-130nm, SMIC65-130nm, Altis130RF,HV,S2
  • EDA and Verification tools: Mentor Graphics tools: Calibre; Synopsys tools: CosmosSE, CosmosLE, Custom Designer, Hercules, Star-RCXT, HSPICE, Lynx Design System; Cadence tools: Virtuoso, PVS(Physical Verification System); Agilent tools: Advanced Design System (ADS), Momentum (electromagnetic simulator), Vivado Design Suite (for Xilinx FPGA design and verification)
  • Operating Systems: Windows 7/XP/2003, Linux 9.0/RHL4.0/5.0, Unix
  • Scripting Languages: csh, bash, Perl, Tcl/Tk, Python, skill.
  • Programming Languages:  Pascal, C/C++.
  • EDA languages/formats: SPICE, LEF, LIB.
  • Windows Applications: MS Office 2003/2007, Adobe Acrobat 10.0, Internet Explorer, Mozilla Web Browser, Thunderbird email client.
  • Linux Applications: Open Office 1.1, Acrobat Reader, Kmail, Mozilla email & Web Browser, Thunderbird email client.
  • Version and Revision Control Systems: SVN, Perforce
  • Issue & Project Tracking: JIRA
 

Core competence:
  • Electrical Engineering & Computer Sciences (Integrated Circuits)
  • VLSI Design
  • Analog / Digital Integrated Circuits
  • IC Devices
  • Microelectronic Circuits and Devices
  • Analog  Mixed-Signal Circuits
  • Scripting Languages: Perl, Tcl, Python, bash, csh, tclsh
  • Programming Languages: C/C++
  • Design data formats: LEF, LIB, GDS, OA

Languages

EnglishFluentRussianNative speakerAmharicNative speaker

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