08/31/2025 updated
IG
100 % available
Senior Analog/Mixed-Signal IC Design Engineer, Senior IC Design Engineer
Reutov, Russian Federation
Worldwide
M ScMicrosoft WindowsAnalogue ElectronicsAtlassian JiraLinuxIntegrated Circuit DesignDigital LibrariesCadence VirtuosoSubversionUSBVerilogVideo EncodingLinux Virtual ServerParallel Patterns LibraryComplementary Metal-Oxide Semiconductor (CMOS)Executive Control Language
IPs, ASIC, USB 2.0 transceiver IP, PHY, CMOS, comparators, LDOs, HID, sensor, Verilog, PPL, analog circuits, video encoding, digital library, ECL, FireWire, Cadence Virtuoso Schematics, ADE L/XL, Spectre, PVS LVS, Quantus, PEX, Cliosoft SOS, Atlassian Jira+Confluence, svn Lab, Linux, Windows experienced user, Cadence Encounter, Verilog-A, Synopsys DC, Microwave Office
Experience
Professional experience10+ years
Freelancer since2018
Languages
EnglishFluentRussianNative speaker
Project history
Digital Solutions (Lead Russian ASIC design company, www.dsol.ru )
I was responsible for leading the analog/mixed-signal IPs development for various ASICs and SoCs
that were designed by the company ranging from system architecture and technical specifications
through schematics development, spice simulation, layout design guidance to post layout netlists
extraction and simulation. Besides, I guided lab evaluation and issue investigation.
In addition, I was responsible for the project technical lead and for a small design team management.
Some of the projects:
* Rad Hardened by Design SerDes PHY IPs for 1.25Gbps and 3.125Gbps serial interfaces in
0.18um and 90nm. I performed overall system architecture design, supervised the development
of all the blocks and also designed the phase interpolator and samplers for the CDR. The main
challenge was that despite the overall performance to be obtained different techniques should be
used for radiation hardening. The IPs had been proven in silicon and ready for SoC integration.
* Rad Hardened by Design direct digital synthesizer (DDS) for aerospace radio applications in
0.18um CMOS. I designed 12-bit 300MSPS current steering DAC and led the design of AD-
PLL and current reference with BGAP. The IC was ready for mass production.
* USB 2.0 transceiver IP (PHY) in 0.18um LP CMOS for Russian fab. I led the development of all
analog blocks. The IP had been proven in silicon and ready for SoC integration.
* ASIC with extremely low power consumption in 0.18um CMOS with comparators, LDOs, 8-bit
SAR ADC, voltage and current sources, oscillator and small control circuit. I was responsible for
definition and led the design. The ASIC was ready for mass production.
* Heavy Ions Detector for aerospace missions was based on modified asymmetrical SRAM cells
in 0.18um CMOS. It includes SRAM-like arrays based on different types of sensitive cells to
detect heavy ions with different energies. Each array includes an in-column readout circuit and a
controller for fast read/write operations. I designed a set of sensitive cells and was responsible
for the overall design definition. HID was ready for mass production for Russian Space Agency.
http://eng.dsol.ru/projects/asic_design/hi_sensor/
* HV ASIC with LVDS interface in 0.25um BCD CMOS technology. The developed blocks
include an LVDS receiver, HV power switches with over temperature and over current
protection circuits, level shifters, BGAP and LDO circuits. ASIC was in production as a small
engineering lot. http://eng.dsol.ru/projects/asic_design/driver/
* For other aerospace projects I designed and characterized a basic RHBD standard cell and an IO
libraries and supervised the design of SRAM blocks in bulk 0.18um CMOS technology.
* I designed several 60-80MHz RC-oscillators with the frequency calibrated to within +/-1% and
several 2-10MHz RC-oscillators for low power controller state in 0.18um and 65nm CMOS.
I was responsible for leading the analog/mixed-signal IPs development for various ASICs and SoCs
that were designed by the company ranging from system architecture and technical specifications
through schematics development, spice simulation, layout design guidance to post layout netlists
extraction and simulation. Besides, I guided lab evaluation and issue investigation.
In addition, I was responsible for the project technical lead and for a small design team management.
Some of the projects:
* Rad Hardened by Design SerDes PHY IPs for 1.25Gbps and 3.125Gbps serial interfaces in
0.18um and 90nm. I performed overall system architecture design, supervised the development
of all the blocks and also designed the phase interpolator and samplers for the CDR. The main
challenge was that despite the overall performance to be obtained different techniques should be
used for radiation hardening. The IPs had been proven in silicon and ready for SoC integration.
* Rad Hardened by Design direct digital synthesizer (DDS) for aerospace radio applications in
0.18um CMOS. I designed 12-bit 300MSPS current steering DAC and led the design of AD-
PLL and current reference with BGAP. The IC was ready for mass production.
* USB 2.0 transceiver IP (PHY) in 0.18um LP CMOS for Russian fab. I led the development of all
analog blocks. The IP had been proven in silicon and ready for SoC integration.
* ASIC with extremely low power consumption in 0.18um CMOS with comparators, LDOs, 8-bit
SAR ADC, voltage and current sources, oscillator and small control circuit. I was responsible for
definition and led the design. The ASIC was ready for mass production.
* Heavy Ions Detector for aerospace missions was based on modified asymmetrical SRAM cells
in 0.18um CMOS. It includes SRAM-like arrays based on different types of sensitive cells to
detect heavy ions with different energies. Each array includes an in-column readout circuit and a
controller for fast read/write operations. I designed a set of sensitive cells and was responsible
for the overall design definition. HID was ready for mass production for Russian Space Agency.
http://eng.dsol.ru/projects/asic_design/hi_sensor/
* HV ASIC with LVDS interface in 0.25um BCD CMOS technology. The developed blocks
include an LVDS receiver, HV power switches with over temperature and over current
protection circuits, level shifters, BGAP and LDO circuits. ASIC was in production as a small
engineering lot. http://eng.dsol.ru/projects/asic_design/driver/
* For other aerospace projects I designed and characterized a basic RHBD standard cell and an IO
libraries and supervised the design of SRAM blocks in bulk 0.18um CMOS technology.
* I designed several 60-80MHz RC-oscillators with the frequency calibrated to within +/-1% and
several 2-10MHz RC-oscillators for low power controller state in 0.18um and 65nm CMOS.
SensorIS (IC design company, subsidiary of Unique ICs, www.uniqueics.com )
I was responsible for management of the IC Layout Design and Verification Department (4 layout
design engineers), interaction with Silicon Fabs on technical and technological issues as well with IP
providers, preparation and tapeout project data to the Fabs for MPW, MLM and mass production.
During the work period 7 MPWs, 2 MLMs and 2 mass-produced ICs were successfully taped out.
Under my leadership layout designs of 6 ICs were developed. In addition, I carried out the most
critical and time consuming DRC and LVS verifications for these ICs.
I was responsible for management of the IC Layout Design and Verification Department (4 layout
design engineers), interaction with Silicon Fabs on technical and technological issues as well with IP
providers, preparation and tapeout project data to the Fabs for MPW, MLM and mass production.
During the work period 7 MPWs, 2 MLMs and 2 mass-produced ICs were successfully taped out.
Under my leadership layout designs of 6 ICs were developed. In addition, I carried out the most
critical and time consuming DRC and LVS verifications for these ICs.
Unique ICs (IC design company, www.uniqueics.com , only in russian)
I was responsible for analog and mixed-signal blocks design for high-speed interface IPs, as well as
for other high-speed applications. My responsibilities included circuit design, simulations (pre- and
post-layout) and layout design guidance, complex IC evaluation with the Characterization Department,
small digital circuits design in Verilog RTL, logic synthesis, behavioral and logic modeling
with NCVerilog, development of a digital circuit layout (up to 2000 gates for All-Digital PPL).
I designed analog circuits for the USB2.0 PHY, DVI PHY as IPs, including AD-PLLs for them (up to
1500MHz), cable repeater USB1.1 (the chip was sold as UIC4102CP). The USB 2.0 PHY IP was
used in SoCs like an USB token, a video encoding processor designed by the company.
I also designed and characterized a basic digital library in 0.18um CMOS used in the company ASIC
designs and characterized a basic ECL digital library in 0.13um SiGe BiCMOS.
I was responsible for analog and mixed-signal blocks design for high-speed interface IPs, as well as
for other high-speed applications. My responsibilities included circuit design, simulations (pre- and
post-layout) and layout design guidance, complex IC evaluation with the Characterization Department,
small digital circuits design in Verilog RTL, logic synthesis, behavioral and logic modeling
with NCVerilog, development of a digital circuit layout (up to 2000 gates for All-Digital PPL).
I designed analog circuits for the USB2.0 PHY, DVI PHY as IPs, including AD-PLLs for them (up to
1500MHz), cable repeater USB1.1 (the chip was sold as UIC4102CP). The USB 2.0 PHY IP was
used in SoCs like an USB token, a video encoding processor designed by the company.
I also designed and characterized a basic digital library in 0.18um CMOS used in the company ASIC
designs and characterized a basic ECL digital library in 0.13um SiGe BiCMOS.