07/08/2026 updated
100 % available
Senior Analog/Mixed-Signal Layout Engineer | 14+ Years | Cadence Virtuoso | Remote B2B
Seoul, South Korea
Only remote
B.S. in Electrical Engineering, Cheongju UniversityAbout me
Work Arrangement • Fully remote from Korea (UTC+9) • B2B contract engagement available (active business entity) • Comfortable with asynchronous communication via email, Slack, and Microsoft Teams • Flexible working hours with willingness to align with European (CET) and US time zones
Python (Programming Language)
Full-Custom AMS Layout with Cadence Virtuoso
Over 14 years of full-custom analog and mixed-signal layout experience using Cadence Virtuoso and Calibre, covering end-to-end AMS layout flow from planning through implementation, verification, and tape-out.
Wireless and RF Product Layout
Extensive experience with wireless and RF product layout including Bluetooth and Wi-Fi (2.4GHz / 5GHz), with strong expertise in precision matching, shielding, guard rings, and noise isolation techniques for sensitive analog/RF blocks.
Advanced Process Node Experience
Solid experience on advanced process nodes including Samsung 16nm FinFET, GlobalFoundries 28nm/55nm, TSMC 28nm, SMIC 28nm, UMC 28nm/40nm, and various other nodes ranging from 16nm to 180nm across multiple foundries.
Block-Level Layout Expertise
Deep expertise in layout of data converters (ADC, DAC), core analog blocks (Comparator, OTA, Amplifier, Current Mirror, Oscillator, BGR), power management blocks (LDO, Charge Pump, DC-DC), and interface blocks (PLL, MIPI, SerDes).
CIS and ROIC Layout
Specialized experience in image sensor layout including CIS and ROIC, covering readout circuits, pitched layout (pixel-aligned), and layout under Metal-4 process constraints.
Design Environment Setup and PDK Management
Experience with design environment setup using csh and bash scripting, PDK installation and maintenance, and design data management using IC Manage and ClioSoft SOS in multi-site environments.
Sign-Off Level Verification Flows
Full-chip padframe layout and verification including ERC and soft-check flows, with end-to-end ownership of AMS layout verification at sign-off level using Virtuoso-based flows.
Noise Reduction and Layout Optimization
Proven track record in layout-driven optimization, including reducing switching noise from 3.2V to 720mV, improving matching accuracy in high-sensitivity analog blocks, and increasing diode insertion across nets from 800 to 1000.
Technical Scope: CMOS, BCDMOS, BiCMOS
Coverage of CMOS, BCDMOS, and BiCMOS technologies ranging from -30V to +30V, with end-to-end AMS layout from sub-block to macro to full-chip level.
Over 14 years of full-custom analog and mixed-signal layout experience using Cadence Virtuoso and Calibre, covering end-to-end AMS layout flow from planning through implementation, verification, and tape-out.
Wireless and RF Product Layout
Extensive experience with wireless and RF product layout including Bluetooth and Wi-Fi (2.4GHz / 5GHz), with strong expertise in precision matching, shielding, guard rings, and noise isolation techniques for sensitive analog/RF blocks.
Advanced Process Node Experience
Solid experience on advanced process nodes including Samsung 16nm FinFET, GlobalFoundries 28nm/55nm, TSMC 28nm, SMIC 28nm, UMC 28nm/40nm, and various other nodes ranging from 16nm to 180nm across multiple foundries.
Block-Level Layout Expertise
Deep expertise in layout of data converters (ADC, DAC), core analog blocks (Comparator, OTA, Amplifier, Current Mirror, Oscillator, BGR), power management blocks (LDO, Charge Pump, DC-DC), and interface blocks (PLL, MIPI, SerDes).
CIS and ROIC Layout
Specialized experience in image sensor layout including CIS and ROIC, covering readout circuits, pitched layout (pixel-aligned), and layout under Metal-4 process constraints.
Design Environment Setup and PDK Management
Experience with design environment setup using csh and bash scripting, PDK installation and maintenance, and design data management using IC Manage and ClioSoft SOS in multi-site environments.
Sign-Off Level Verification Flows
Full-chip padframe layout and verification including ERC and soft-check flows, with end-to-end ownership of AMS layout verification at sign-off level using Virtuoso-based flows.
Noise Reduction and Layout Optimization
Proven track record in layout-driven optimization, including reducing switching noise from 3.2V to 720mV, improving matching accuracy in high-sensitivity analog blocks, and increasing diode insertion across nets from 800 to 1000.
Technical Scope: CMOS, BCDMOS, BiCMOS
Coverage of CMOS, BCDMOS, and BiCMOS technologies ranging from -30V to +30V, with end-to-end AMS layout from sub-block to macro to full-chip level.
Experience
Professional experience10+ years
Freelancer since2011
Languages
EnglishGoodKoreanFluent
Project history
Analog layout