06/06/2024 updated
SL
100 % available
Senior FPGA Design Engineer
India
Worldwide
B.Tech Electronics and CommunicationAlgorithmsArchitectureAutomationC++ (Programming Language)Printed Circuit BoardCode GenerationCommunicationMicroarchitectureDigital MarketingField-Programmable Gate Array (FPGA)Hardware Description LanguageHardware DesignPython (Programming Language)LithographyMaster/Slave
- Hardware Implementation of SHA3-256 hash algorithm in Verilog on Xilinx Ultrascale+ fpga VCU1525 Acceleration Development kit for mining SmartCash coin(cryptocurrency).
- Hardware Implementation of SHA2-256 hash algorithm in Verilog on Xilinx Ultrascale+ fpga VCU1525 Acceleration Development kit for mining Bitcoin (cryptocurrency).
- Hardware Implementation of keccak800 hash algorithm in Verilog on Xilinx Ultrascale+ fpga VCU1525 Acceleration Development kit for mining Odocrypt coin(cryptocurrency).
- Hardware Implementation of Eaglesong hash algorithm in Verilog on Xilinx Ultrascale+ fpga VCU1525 Acceleration Development kit for mining Nervous (CKB)coin(cryptocurrency).
- Hardware Implementation of Ethash hash algorithm in Verilog on Xilinx Ultrascale+ fpga VCU1525 Acceleration Development kit for mining Ethereum coin(cryptocurrency).
- Hardware Implementation of Ethash hash algorithm in Verilog on Xilinx Ultrascale+ fpga xcvu33p-fsvh2104 with HBM for mining Ethereum coin (cryptocurrency).
- Hardware Implementation of OFDM transmitter and OFDM receiver on Digilent zybo z7-20 fpga development board using MATLAB Simulink and HDL code generator.
- Implementation of HDMI PHY on artix-7 fpga for custom video processing fpga board for commercial use.
- Working closely with PCB hardware design team for designing custom board. Developing roadmap for custom board bring up as per specification.
- Developing projects to verify all bus interface are working with IIC, SPI, UART, HDMI, DDR3 etc. with microblaze soft-processor for custom board.
- Designing micro-architecture of algorithms on fpga. Implementing hash algorithm with fully-unrolled and pipelined architecture to achieve maximum throughput and fabric clock frequency ranging from 300MHz to 550MHz.
- Handling Cross-Clock Domain and STA analysis on failing nets, familiar with synthesis and implementation constraints. Designing block level design (IPI design) using Xilinx Vivado software tool.
- Developing custom IPs in Verilog with AMBA AXI4 protocol such as AXI4 stream(master/slave), AXI4-lite(slave), AXI4(master) to communicate to other IP’s.
- Developing custom IPs in c/c++ using Xilinx Vitis hls software with AMBA AXI4 protocol such as AXI4 stream(master/slave), AXI4-lite(slave), AXI4(master) to communicate to other IP’s.
- Developing tcl script for design automation from creating Vivado project to bitstream. Implementation of PCIe interface using xdma_pcie ip from Xilinx for sending and receiving data from host to card and card to host on fpga that supports PCIe bus.
- Familiar with design and implementation of on Chip HBM(Highbandwith memory) and off Chip DDR3/DDR4 external memory interface.
- Developing host software multithreaded application in python to communicate to server and FPGA.
- Writing technical content for the projects developed on company website and other third-party websites for digital marketing and SEO.
- Planning and development of projects from RFQ’s.
Experience
Professional experience5 - 10 years
Freelancer since2020
Languages
EnglishFluent