10/29/2026 updated
100 % available
System Architect | RISC-V Hardware/Software Co-Design | Compilers for ML Accelerators
T, Romania
Worldwide
Politehnica University of Timisoara, Romania (1992-1997)CompilersEmbedded SystemsField-Programmable Gate Array (FPGA)Hardware DesignSoftware ArchitecturePrototypingRequirements EngineeringReduced Instruction Set ComputingSystemVerilog
RTL Design & RISC-V ISA Extension
Expertise in RTL design including RISC-V ISA extensions using the lowRISC Ibex core, OpenHW CV-X-IF coprocessor interface, and hardware accelerator integration with platforms such as RedMulE and PULP. Design and simulation using SystemVerilog, Verilator, Questa, and slang.
Compiler Frameworks (LLVM/Clang & ONNX-MLIR)
Development of custom compiler toolchains using LLVM/Clang for RISC-V backend extensions including TableGen, MC layer, and target builtins. Extension of ONNX-MLIR with custom MLIR dialects and lowering passes for mapping workloads onto hardware accelerators.
FPGA Prototyping
Prototyping of SoCs on FPGA using AMD Vivado with Zynq UltraScale+ ZCU104 boards and Vitis HLS. Scripted project generation, timing and pin constraints, JTAG program upload, and UART-based result viewers.
Logic Synthesis
Exploratory logic synthesis using Yosys with ABC, IHP SG13G2 130nm open PDK standard cells, and SDC timing constraints.
Hardware Design (High-Level Synthesis)
Hardware design using SystemVerilog and High-Level Synthesis with C++, enabling efficient hardware/software co-design workflows.
Programming (C++, C, Python)
Proficient programming in C++, C, and Python, applied across embedded systems, automotive software, compiler development, and hardware design automation.
Scripting & EDA Tool Automation
Scripting with Tcl for EDA tool automation and Bash for build and workflow automation, including CMake, Make, FuseSoC, and Bender.
Machine Learning Frameworks
Exploratory use of ONNX and PyTorch for machine learning workloads, including mapping GEMM and complex GEMM operations onto hardware accelerators via custom MLIR dialects.
System Architecture & Requirements Engineering
System-level architecture design and modelling across hardware and software for automotive products and research prototypes. Certified Professional for Requirements Engineering (IREB Foundation Level). Use of PREEVision and Rhapsody (UML) for architecture modelling.
Software Architecture & Object-Oriented Design
Design and development of software architectures using UML, OOA/OOD, and model-driven development with Rhapsody. Experience in C++ Windows applications, client-server architectures, and web-based systems using Java EE, GWT, AJAX, and CORBA/IDL middleware.
Expertise in RTL design including RISC-V ISA extensions using the lowRISC Ibex core, OpenHW CV-X-IF coprocessor interface, and hardware accelerator integration with platforms such as RedMulE and PULP. Design and simulation using SystemVerilog, Verilator, Questa, and slang.
Compiler Frameworks (LLVM/Clang & ONNX-MLIR)
Development of custom compiler toolchains using LLVM/Clang for RISC-V backend extensions including TableGen, MC layer, and target builtins. Extension of ONNX-MLIR with custom MLIR dialects and lowering passes for mapping workloads onto hardware accelerators.
FPGA Prototyping
Prototyping of SoCs on FPGA using AMD Vivado with Zynq UltraScale+ ZCU104 boards and Vitis HLS. Scripted project generation, timing and pin constraints, JTAG program upload, and UART-based result viewers.
Logic Synthesis
Exploratory logic synthesis using Yosys with ABC, IHP SG13G2 130nm open PDK standard cells, and SDC timing constraints.
Hardware Design (High-Level Synthesis)
Hardware design using SystemVerilog and High-Level Synthesis with C++, enabling efficient hardware/software co-design workflows.
Programming (C++, C, Python)
Proficient programming in C++, C, and Python, applied across embedded systems, automotive software, compiler development, and hardware design automation.
Scripting & EDA Tool Automation
Scripting with Tcl for EDA tool automation and Bash for build and workflow automation, including CMake, Make, FuseSoC, and Bender.
Machine Learning Frameworks
Exploratory use of ONNX and PyTorch for machine learning workloads, including mapping GEMM and complex GEMM operations onto hardware accelerators via custom MLIR dialects.
System Architecture & Requirements Engineering
System-level architecture design and modelling across hardware and software for automotive products and research prototypes. Certified Professional for Requirements Engineering (IREB Foundation Level). Use of PREEVision and Rhapsody (UML) for architecture modelling.
Software Architecture & Object-Oriented Design
Design and development of software architectures using UML, OOA/OOD, and model-driven development with Rhapsody. Experience in C++ Windows applications, client-server architectures, and web-based systems using Java EE, GWT, AJAX, and CORBA/IDL middleware.
Experience
Professional experience10+ years
Freelancer since2026
Languages
GermanGoodEnglishFluentRomanianNative speaker
Project history
System architecture design and modelling across hardware and software for automotive products and research prototypes. Led Task 5.2 (Automotive Demonstrator) in the Chips JU ISOLDE project (Horizon Europe), building an extended RISC-V SoC with matrix-multiplication accelerators, FPGA prototype, and compilers. Projects included Vehicle Data Recorder (VDR), Electronic On-Board Recorder (EOBR), EETS study, and Driver's Hours Engine (DHE).
Software architecture for the Digital tachograph product (EU market), recording truck-driver activity data in compliance with Commission Regulation (EC) No 1360/2002. Owned the software architecture of the team's module modelled in UML with Rhapsody, coached the team in OOA/OOD, and acted as Product Owner in the Scrum development process.
Software architect for COR-Life, a platform-independent client-server standard software in C++ for managing life-insurance and pension-fund portfolios. Designed and developed a web-based point-of-sale system on a three-tier architecture and migrated the C++ CORBA middleware from Orbacus to omniORB.