07/18/2025 updated
WM
100 % available
Analog-mixed Layout and Physical IC Design Engineer
cairo, Egypt
Worldwide
Bachelor of electronics and communication engineeringC++ (Programming Language)Computer ProgrammingIntegrated Circuit DesignElectrical DiagramsFloor PlanningPython (Programming Language)Object-Oriented Software DevelopmentPCI ExpressPumpsSimulationsVoltage-Controlled OscillatorVHSIC Hardware Description Language (VHDL)Linux Virtual Server
IC Layout Design
Extensive experience in analog-mixed layout and physical IC design from 2nm to 22nm technology nodes for various manufacturers including TSMC, Samsung, and Intel.
SerDes IP Systems
Expertise in wired SerDes IP systems like PCIe Express and high-speed SerDes (112G, 224G), handling all aspects from kickoff meetings to signoff tapeouts.
Circuit Component Design
Specialized knowledge in LC and RO PLLs, charge pumps, LC Tank VCO, coarse tuning, varactors, loop filters, LDOs and internal regulators with verification experience.
Layout Verification
Proficiency in all types of layout verifications including LVS, DRC, ANT, Aging violations and EMIR simulations to ensure design integrity.
Floorplanning & Optimization
Advanced skills in creating placement and floorplanning recommendations in 2nm technology through various test cases and iterations.
Programming & Tools
Knowledge of C/C++, Python, OOP, VHDL, and proficiency with industry tools like Synopsys Custom Compiler, Cadence, Calibre, StarRC, and PrimeSim EMIR.
Power Integration
Experience in power-mesh design, TSV placement, and ensuring proper power integration across different components while maintaining design rules.
Extensive experience in analog-mixed layout and physical IC design from 2nm to 22nm technology nodes for various manufacturers including TSMC, Samsung, and Intel.
SerDes IP Systems
Expertise in wired SerDes IP systems like PCIe Express and high-speed SerDes (112G, 224G), handling all aspects from kickoff meetings to signoff tapeouts.
Circuit Component Design
Specialized knowledge in LC and RO PLLs, charge pumps, LC Tank VCO, coarse tuning, varactors, loop filters, LDOs and internal regulators with verification experience.
Layout Verification
Proficiency in all types of layout verifications including LVS, DRC, ANT, Aging violations and EMIR simulations to ensure design integrity.
Floorplanning & Optimization
Advanced skills in creating placement and floorplanning recommendations in 2nm technology through various test cases and iterations.
Programming & Tools
Knowledge of C/C++, Python, OOP, VHDL, and proficiency with industry tools like Synopsys Custom Compiler, Cadence, Calibre, StarRC, and PrimeSim EMIR.
Power Integration
Experience in power-mesh design, TSV placement, and ensuring proper power integration across different components while maintaining design rules.
Project history
Working on refloorplanning and routing charge pump and loop filter following established procedures. Handling top-level integration including power mesh integration of charge pump, phase frequency detector and Vrefgen.
Responsible for delivering VCO coarse tuning blocks, top-level integration between charge pump and VCO hierarchy, layout design of loop filter and coarse tuning units, and completing all verifications.
Working on wired SerDes IP systems including PCIe Express and high-speed SerDes (112G, 224G). Responsible for LC and RO PLLs, charge pumps, LC Tank VCO, and various components. Creating placement and floorplanning recommendations in 2nm technology.