Physical Design feasibility study - Porting TSMC to GF40UX

The objective of the assignment is to assess the technical feasibility of the porting activity, identify key challenges and risks, and provide an effort estimation for the required implementation work. The initial feasibility phase is expected to run for approximately three months, with a preferred project start as soon as possible.

We are currently looking for an experienced Physical Design (PD) engineer to support a feasibility study for a potential porting of an existing ASIC from TSMC technology to GlobalFoundries 40UX.

-Senior ASIC Physical Design Engineer (8+ years experience)

-Previous hands-on experience with GlobalFoundries 40nm technology is strongly preferred.

-Proven experience in ASIC technology migration/porting projects is mandatory

-Hands-on experience with complete PD flow: floorplanning, power planning, placement, CTS, routing, timing closure and sign-off

-Experience with Synopsys and/or Cadence digital implementation and sign-off flows

-Experience with foundry technologies, PDK integration and design-rule-driven implementation

-Strong understanding of STA, SI, power integrity, DRC/LVS and physical verification flows

-Experience supporting technology migration or ASIC porting projects between process technologies

-Ability to independently drive Physical Design feasibility assessments and provide technical recommendations with limited supervision

Optional skills:

-Experience with mixed-signal or sensor ASICs

-Knowledge of memory integration and library qualification

-Experience working with external design houses and distributed teams

-Familiarity with Bosch, automotive or industrial semiconductor development environments

-Experience contributing to feasibility studies and effort estimation activities

Tasks:

-Analyze the existing TSMC-based ASIC implementation and identify Physical Design dependencies relevant for migration to GlobalFoundries.

-Assess floorplan, timing, power, clocking and implementation impacts related to the target GlobalFoundries technology.

-Evaluate availability and suitability of standard cell libraries, memory macros, IPs and physical verification infrastructure.

-Assess EDA flow compatibility, implementation methodology and sign-off readiness for the proposed technology environment.

-Identify major technical risks, constraints and blockers affecting physical implementation feasibility.

-Support definition of product-equivalence assumptions and their impact on Physical Design activities.

-Estimate Physical Design complexity, engineering effort, resource requirements and schedule implications.

-Participate in technical reviews with Bosch internal experts and provide recommendations regarding key feasibility questions.

-Contribute to the overall technology-readiness assessment and feasibility documentation.

-Support preparation of implementation scenarios and recommendations for subsequent project phases

-Analyze the existing TSMC-based ASIC implementation and identify Physical Design dependencies relevant for migration to GlobalFoundries.

-Assess floorplan, timing, power, clocking and implementation impacts related to the target GlobalFoundries technology.

-Evaluate availability and suitability of standard cell libraries, memory macros, IPs and physical verification infrastructure.

-Assess EDA flow compatibility, implementation methodology and sign-off readiness for the proposed technology environment.

-Identify major technical risks, constraints and blockers affecting physical implementation feasibility.

-Support definition of product-equivalence assumptions and their impact on Physical Design activities.

-Estimate Physical Design complexity, engineering effort, resource requirements and schedule implications.

-Participate in technical reviews with Bosch internal experts and provide recommendations regarding key feasibility questions.

-Contribute to the overall technology-readiness assessment and feasibility documentation.

-Support preparation of implementation scenarios and recommendations for subsequent project phases