Description
Verification Engineer required by an international leading semiconductor organisation on a long term contract basis. Based in Germany, Verification Engineers will work as part of an established team working on the top level verification of Digital Integrated Circuits(Simulation Digital Design).Responsibilities:
* Working on your own initiative, to complete all development activities in the field of digital front-end design.
* Communicate within a design team and cross-site development organisation.
* Digital designer experience required to generate RTL coding in Verilog and VHDL and perform the logic synthesis.
Scope of work:
* Experience in digital integration and verification of signal processing systems.
* Setup of verification test benches and adapt verification software to the specific needs
* Verify digital designs with dedicated test benches
* Create integration documentation and reports.
Skills Required:
* Top level verification is a must
* Experienced with Cadence 6.1.x Open Access simulation environment.
* Program System C/C++ for testbench generation
* VHDL
* Verilog
* SystemC
* Digital Design and signal processing
This is a long term opportunity working within a cutting edge environment.