Skills
network engine, ASIC Design/Verification, Verilog, FPGA Hardware, ASIC, parsing, SynopsysVCS, VERDI, Cadence Xcelium, Questa ModelSIM v10.0d, Questa SIM v10.2c, cadence nc-sim, Xilinx ISE 14.4i, Xilinx Vivado ALTERA Quartus II 12.0, Synopsys Metaware Debugger, IBM PPC440, ARM CortexM, GREBE, SYNOPSYS ARC, UART, I2C, I3C, SPI, SPEEDY, I2S, AMBA APB, AHB, AXI, IBM PLB, AXI Interconnects, ARM LongHops, TREX, HVL, System Verilog, UVM, Operating System, Linux, Windows, UBOOT, Scripting Languages, Perl, TCL, Neural Network, augmented reality, algorithms, object detection, power efficiency, ASIP, Memory management, DMA, user interface, image processing, CAFFE, FPGA, algorithm, Altera, decoding, firmware, LDPC algorithm/SanDisk LDPC algorithm, Quartus, PCIe, Microblaze, PowerPC, VIRTEX 5 FPGA device, debugging, Flash Memory, X0Y0, Bit File, API, SDK, U-Boot, Regression, TCL script, Perl scripts, Questa simulation, XSDK, co-hardware, software simulation, IBM, Boot Loader, Embedded Hardware, shell script, test case, bug tracker, Vivado, shell, script, boot file, windows shell, Xilinx ISE, Modelsim, Ethernet, PCI, MAC address, QuestaSim10.0b